Boolean port

Discussion in 'VHDL' started by Dan, Dec 1, 2007.

  1. Dan

    Dan Guest

    I'm trying to simulate an entity that has a boolean output port, but
    ModelSim alerts me with this message:

    "Types do not match between component and entity for port <port_name>"

    (Filename "Name_of_my_entity_timesim.vhd" Line 30)

    I opened that file and I notice that the boolean signal is represented as
    std_logic_vector (0 downto 0)

    ?

    I worked around the problem using a std_logic type instead of boolean, but I
    would like to know about other suggestions.

    Is this a known problem when simulating boolean signals?

    Thanks,
    Dan, Dec 1, 2007
    #1
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  2. On Sat, 1 Dec 2007 15:34:12 +0100, "Dan" <> wrote:

    >I'm trying to simulate an entity that has a boolean output port, but
    >ModelSim alerts me with this message:
    >
    > "Types do not match between component and entity for port <port_name>"
    >
    >I opened that file and I notice that the boolean signal is represented as
    >std_logic_vector (0 downto 0)
    >
    >?
    >Is this a known problem when simulating boolean signals?


    It's a known problem when ports on a component and
    an entity are of different type :)

    Was the component automatically generated in some way
    from the entity? If so, the automatic tool is buggy.

    Read my lips: VHDL IS A STRONGLY TYPED LANGUAGE.
    boolean != std_logic
    std_logic != std_logic_vector(0 downto 0)

    There's nothing wrong with using boolean signals, provided
    you are happy for your simulations to use 2-state logic.
    But a port of boolean type can only be connected to a
    signal of boolean type, and so on. And the data types of
    ports on component and entity must match, or else must
    be type-converted in a configuration's port map.

    You may find it's less hassle to use direct instantiation,
    so that you don't use components at all. You then need
    only to concern yourself with matching signal types to
    the types of ports of the entity.
    --
    Jonathan Bromley, Consultant

    DOULOS - Developing Design Know-how
    VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

    Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK

    http://www.MYCOMPANY.com

    The contents of this message may contain personal views which
    are not the views of Doulos Ltd., unless specifically stated.
    Jonathan Bromley, Dec 1, 2007
    #2
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  3. Dan

    Andy Guest

    On Dec 1, 8:34 am, "Dan" <> wrote:
    > I'm trying to simulate an entity that has a boolean output port, but
    > ModelSim alerts me with this message:
    >
    > "Types do not match between component and entity for port <port_name>"
    >
    > (Filename "Name_of_my_entity_timesim.vhd" Line 30)
    >
    > I opened that file and I notice that the boolean signal is represented as
    > std_logic_vector (0 downto 0)
    >
    > ?
    >
    > I worked around the problem using a std_logic type instead of boolean, but I
    > would like to know about other suggestions.
    >
    > Is this a known problem when simulating boolean signals?
    >
    > Thanks,


    If you use a boolean port at the top level of your RTL (synthesizable
    code), then the gate level model will change to std_logic. I suspect
    this may be related to your problem. Are you trying to use a
    configuration to bind your testbench to your gate level model? Look up
    port (or type) conversion functions. They can be called in the port
    map of the UUT in the configuration of your testbench.

    Andy
    Andy, Dec 3, 2007
    #3
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