boolean to std_logic

Discussion in 'VHDL' started by valentin tihomirov, Dec 31, 2003.

  1. Is there any standard package that can convert TRUE to '1' and FALSE to '0'?
    Should I write my function? Why there isn't implicit sythax of that?
    valentin tihomirov, Dec 31, 2003
    #1
    1. Advertising

  2. valentin tihomirov

    Ray Andraka Guest

    This is actually a spin-off of a topic that is being discussed in the VHDL
    standards committee. The rub is that True does not always equate to
    '1'..negative logic systems use '0' = true. A function to do this is
    straight-forward to write.

    valentin tihomirov wrote:

    > Is there any standard package that can convert TRUE to '1' and FALSE to '0'?
    > Should I write my function? Why there isn't implicit sythax of that?


    --
    --Ray Andraka, P.E.
    President, the Andraka Consulting Group, Inc.
    401/884-7930 Fax 401/884-7950
    email
    http://www.andraka.com

    "They that give up essential liberty to obtain a little
    temporary safety deserve neither liberty nor safety."
    -Benjamin Franklin, 1759
    Ray Andraka, Dec 31, 2003
    #2
    1. Advertising

  3. Thanks. I've got a more general answer regarding VHDL. VHDL is a strongly
    typed language; thus, all the type conversions should be explicit. It should
    save one's life, some day. In addition, I've discovered a Boolean type that
    makes code much cleaner allowing to bypass the conversion in most cases.
    valentin tihomirov, Jan 1, 2004
    #3
  4. Mike Treseler, Jan 5, 2004
    #4
    1. Advertising

Want to reply to this thread or ask your own question?

It takes just 2 minutes to sign up (and it's free!). Just click the sign up button to choose a username and then you can ask your own questions on the forum.
Similar Threads
  1. Christopher Bunk

    Synthesis of STD_LOGIC

    Christopher Bunk, Jul 1, 2003, in forum: VHDL
    Replies:
    2
    Views:
    1,300
    Tim Hubberstey
    Jul 4, 2003
  2. David R Brooks

    Re: boolean to std_logic

    David R Brooks, Dec 31, 2003, in forum: VHDL
    Replies:
    0
    Views:
    2,469
    David R Brooks
    Dec 31, 2003
  3. J Leonard
    Replies:
    4
    Views:
    12,663
    Mark Space
    Jan 19, 2008
  4. manolis kaliorakis

    convert boolean to std_logic

    manolis kaliorakis, Dec 17, 2011, in forum: VHDL
    Replies:
    2
    Views:
    4,053
    manolis kaliorakis
    Dec 17, 2011
  5. Metre Meter
    Replies:
    7
    Views:
    363
    Metre Meter
    Aug 6, 2010
Loading...

Share This Page