boolean to std_logic

V

valentin tihomirov

Is there any standard package that can convert TRUE to '1' and FALSE to '0'?
Should I write my function? Why there isn't implicit sythax of that?
 
R

Ray Andraka

This is actually a spin-off of a topic that is being discussed in the VHDL
standards committee. The rub is that True does not always equate to
'1'..negative logic systems use '0' = true. A function to do this is
straight-forward to write.

valentin said:
Is there any standard package that can convert TRUE to '1' and FALSE to '0'?
Should I write my function? Why there isn't implicit sythax of that?

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email (e-mail address removed)
http://www.andraka.com

"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
 
V

valentin tihomirov

Thanks. I've got a more general answer regarding VHDL. VHDL is a strongly
typed language; thus, all the type conversions should be explicit. It should
save one's life, some day. In addition, I've discovered a Boolean type that
makes code much cleaner allowing to bypass the conversion in most cases.
 

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