BRAM init (again ?!)

Discussion in 'VHDL' started by Michel Bieleveld, Aug 14, 2004.

  1. Hi I am trying to get initialization to work for BRAM on a spartan 2e.
    I already read a lot of posts about this but till so far, maybe due to
    my lack of understanding, found a solution. This is what i have so
    far, see code, but all i get is a bram initialized to zeros :(

    Michel.



    architecture RTL of ax88796 is
    component RAMB4_S16

    generic (
    INIT_00 : bit_vector :=
    X"000000000000000000000000000000000000000000000000000000000000");


    port (DI : in STD_LOGIC_VECTOR (15 downto 0);
    EN : in STD_logic;
    WE : in STD_logic;
    RST : in STD_logic;
    CLK : in STD_logic;
    ADDR : in STD_LOGIC_VECTOR (7 downto 0);
    DO : out STD_LOGIC_VECTOR (15 downto 0));
    end component;

    attribute INIT_00 : string;
    attribute INIT_00 of rom_ax:label is
    "1001200210012002100120021001200210012002100120021001200210012002";


    begin

    rom_ax : RAMB4_S16

    generic map (
    INIT_00 =>

    X"1001200210012002100120021001200210012002100120021001200210012002"
    )

    port map(X"0000",'1','0','0',CLK,ax_rom_addr,ax_rom_data);
    Michel Bieleveld, Aug 14, 2004
    #1
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  2. Mike Treseler, Aug 17, 2004
    #2
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