BRAM

Discussion in 'VHDL' started by noddy, Mar 7, 2006.

  1. noddy

    noddy Guest

    Hi,

    I was wondering could anyone give me some advice regarding implementing
    a BRAM as a line delay in VHDL. Any advice or sample code would be
    greatly appreciated.

    Thanks for your help

    Noddy
     
    noddy, Mar 7, 2006
    #1
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  2. noddy wrote:

    > I was wondering could anyone give me some advice regarding implementing
    > a BRAM as a line delay in VHDL.


    I would design a BRAM sync fifo with one
    write/push port and one read/pop port.
    Add a controller process to shift the bits
    in and out.

    -- Mike Treseler
     
    Mike Treseler, Mar 7, 2006
    #2
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  3. noddy

    noddy Guest

    I'm really pretty new to this...how would i go about doing that?

    Thanks for your help,

    it is really appreciated

    Noddy
     
    noddy, Mar 8, 2006
    #3
  4. noddy wrote:
    > I'm really pretty new to this...how would i go about doing that?


    get_a_synthesis_manual;
    get_a_simulator;
    get_a_book;
    while not done loop
    search_google_groups;
    check_in_book;
    sketch_some_boxes_and_arrows;
    write_some_code;
    simulate;
    edit_code;
    simulate;
    end loop;
    run_synthesis;

    -- Mike Treseler
     
    Mike Treseler, Mar 8, 2006
    #4
  5. noddy

    Brandon Guest

    Don't be so lazy! Do it for him! :)
     
    Brandon, Mar 8, 2006
    #5
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