buffer port

[Max]

I have this files:

------ main.vhd---------------
entity main is
Port ( sig : buffer std_logic);
end main;

architecture Behavioral of main is

component a is
Port ( siga : in std_logic);
end component;
component b is
Port ( sigb : out std_logic);
end component;

begin
aa: component a
Port map( siga => sig);
bb: component b
Port map ( sigb => sig); -- here is the error
end Behavioral;
--
----------- a.vhd --------------------
entity a is
Port ( siga : in std_logic);
end a;
architecture Behavioral of a is
begin

end Behavioral;
--
----------- b.vhd --------------------
entity b is
Port ( sigb : out std_logic);
end b;
architecture Behavioral of b is
begin
sigb <= '1';
end Behavioral;
--

I obtain the following error in synthesis:
ERROR:HDLParsers:1411 - main.vhd Line XX. Parameter sig of mode buffer
can not be associated with a formal port of mode out.

Buffer port is the same of out port, but can be read from within the
entity, isn't it?
So why occurs this error.

thanks

 

[Egbert Molenkamp]

Max,

You will find your answer in the faq
http://www.vhdl.org/vi/comp.lang.vhdl/FAQ1.html#buffer_ports

Egbert Molenkamp