Building Delay Elements

Discussion in 'VHDL' started by Steven Archibald, Feb 26, 2004.

  1. I am trying to implement the Xilinx DDR SDRAM memory contoller detailed in
    XAPP253 and am having problems with the data strobe line during a read
    cycle. I need to somehow add a delay onto the incoming data strobe signal.
    In Xilinx apllication note 688 it describes a way of building delay elements
    using LUTs. Does anybody know how this can be implemented? I am programming
    in VHDL and targeting a Virtex II Pro.
     
    Steven Archibald, Feb 26, 2004
    #1
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