Bus Emulation in Testbenches

Discussion in 'VHDL' started by PeterHawk, Aug 27, 2009.

  1. PeterHawk

    PeterHawk

    Joined:
    Aug 27, 2009
    Messages:
    1
    Location:
    Aarhus, Denmark
    Hi!

    I'm looking for a nice way to emulate a bus (or another interface) i a VHDL testbench.

    I have a design that interfaces to a bus, and would like to test it functionally from a "relatively" high layer of abstraction.

    In the end I would like the ability to simply write:
    WRITE(<address>, <data>); -- Input a constant and write it to the bus interface according to spec.
    READ(<address>); -- read data from the bus interface according to spec and output result to testbench console/IO

    The bus interface signals is given by the UUT entity.

    I tried placing the READ/WRITE procedures in a separate package, but ended up having to pass all bus- data, address and control signals. i.e:
    WRITE(<wraddress>, <wrdata>, data, address, cs, wr, bs,...);

    Another option is to define the UUT entity signals as global in a separate package, and include this package in the TB and in the bus emulator package. Next problem is how to access the global signals from within the package or rather from within a procedure. Reading global signals from within a procedure is fine, but assigning a value to them does not work.

    I may be on a totally wrong track, but does anyone have a good idea on how to achieve something like this?

    Thanks,

    Peter
     
    PeterHawk, Aug 27, 2009
    #1
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