bus error

[sophia.agnes]

Dear all,

I was going through peter van der linden's book expert C programming
there i found the following section on bus error

a few years ago bus errors were also generated if a memory parity
error was detected.These days memory chips are so reliable , and so
well protected by error detection and correction circuitry, that
parity errors are almost un heard of at the application programming
level.

how true is the above explanation and that can any one give example
code for generating memory parity error ?


a bus error can also be generated by referencing a memory that do not
physically exists

i tried this example:-

int *p = (int*)(-3);
*p =17;

but i am getting only segmentation fault.

what could be proper example for the above statements

 

[santosh]

Dear all,

I was going through peter van der linden's book expert C programming
there i found the following section on bus error

a few years ago bus errors were also generated if a memory parity
error was detected.These days memory chips are so reliable , and so
well protected by error detection and correction circuitry, that
parity errors are almost un heard of at the application programming
level.

how true is the above explanation and that can any one give example
code for generating memory parity error ?

For general computer questions like this try <or
<This has nothing much to do with
Standard C.

a bus error can also be generated by referencing a memory that do not
physically exists

Under certain system's yes. Such details are always architecture
specific, so you cannot generalise.

i tried this example:-

int *p = (int*)(-3);
*p =17;

but i am getting only segmentation fault.

what could be proper example for the above statements

<OT>
I suppose a misalinged attempt at access might generate a bus error.
</OT>

 

[santosh]

Dear all,

I was going through peter van der linden's book expert C programming
there i found the following section on bus error

a few years ago bus errors were also generated if a memory parity
error was detected.These days memory chips are so reliable , and so
well protected by error detection and correction circuitry, that
parity errors are almost un heard of at the application programming
level.

how true is the above explanation and that can any one give example
code for generating memory parity error ?


a bus error can also be generated by referencing a memory that do not
physically exists

<snip>

Instead of asking every question that pops up in your mind at
<try doing a simple web search first. Often the
information you want will be available at various places on the WWW.
For example for bus error a Google search yields the following links,
among others:

<http://en.wikipedia.org/wiki/Bus_error>
<http://web.mit.edu/answers/unix/unix_bus_or_seg.html>
<http://c.ittoolbox.com/documents/popular-q-and-a/bus-error-vs-segmentation-error-2235>

 

[CBFalconer]

I was going through peter van der linden's book expert C programming
there i found the following section on bus error

a few years ago bus errors were also generated if a memory parity
error was detected.These days memory chips are so reliable , and so
well protected by error detection and correction circuitry, that
parity errors are almost un heard of at the application programming
level.

how true is the above explanation and that can any one give example
code for generating memory parity error ?

Parity systems only detect _some_ memory errors, and do not
correct. Good modern systems use ECC, which corrects single bit
errors immediately, and detects at least double bit errors, and
probably most bigger errors. Lousy modern systems omit the ECC.

ECC protects against such things as cosmic rays. Systematic errors
are rare, and detectable through such things as memtest86. But
random events, fixed by ECC, can cause total destruction, and the
evils may happen much later when all backups are fouled.

BTW, is your shift key broken?

 

[Richard Tobin]

a few years ago bus errors were also generated if a memory parity
error was detected.These days memory chips are so reliable , and so
well protected by error detection and correction circuitry, that
parity errors are almost un heard of at the application programming
level.

Actually, the vast majority of modern computers do not have any error
detection of this kind for their main memory. Modern memory is less
susceptible to errors because of improvements in chip packaging which
have reduced the rate of errors due to alpha particles.

-- Richartd

 

[Mark McIntyre]

Dear all,

a few years ago bus errors were also generated if a memory parity
error was detected.These days memory chips are so reliable , and so
well protected by error detection and correction circuitry, that
parity errors are almost un heard of at the application programming
level.

how true is the above explanation and that can any one give example
code for generating memory parity error ?

This isn't a C question. you need to find a better place to ask. Google
for instance...

 

[Tor Rustad]

[sorry being OT, but I do have a weak spot for faults]

On bus error, just take the train.

Parity systems only detect _some_ memory errors, and do not

The point, is that parity bit detect *all* single bit errors, in fact
parity detect all odd bit errors... right?

correct. Good modern systems use ECC, which corrects single bit
errors immediately, and detects at least double bit errors, and
probably most bigger errors.

Good systems, or let say expensive systems, do far more than that.
Recovering *only* from single bit errors, is low-end server stuff.

IBM S/390 mainframes protect against memory failures by design, no chip
affect more than a single bit in the ECC code. Hence, IBM mainframes can
protect against memory chip failures, even in the case that every bit in
a chip fails. That is, the ECC logic can fix hardware fault of a memory
chip, without loss of data.

HP Nonstop (former Tandem Computers) mainframes did protection via
lockstep, is case of HW faults, redundant HW took over the processing.
The principle here, as I understand it, was that computations was
performed in parallel and checked, whenever there was a disagreement,
the module was marked faulty, and processing moved elsewhere from the
last check-point state.

Likewise, various high-end servers, provide extended protection e.g.
chipkill (IBM), chipspare (HP), Extended ECC (Sun/Fijutsi) etc..


These days, Intel Itanium2 CPUs comes with a number of RAS features,
including lock-step technology for both sockets and core. I have tried
reading Intels CPU manuals, without finding much information about these
interesting features.

Both AMD64 and IA-64 has 4 protection rings, while the most popular OS
kernels utilize only two (user and kernel space). Utilizing all the 4
rings, will make future kernels more robust and secure.

ECC protects against such things as cosmic rays. Systematic errors
are rare, and detectable through such things as memtest86. But
random events, fixed by ECC, can cause total destruction, and the
evils may happen much later when all backups are fouled.

HW faults will bring most low-end systems down, correcting single-bit
failures was perhaps sufficient in the past, we do move forward.

 

[CBFalconer]

CBFalconer wrote:
.... snip ...

[sorry being OT, but I do have a weak spot for faults]

Parity systems only detect _some_ memory errors, and do not

The point, is that parity bit detect *all* single bit errors, in
fact parity detect all odd bit errors... right?

correct. Good modern systems use ECC, which corrects single bit
errors immediately, and detects at least double bit errors, and
probably most bigger errors.

Good systems, or let say expensive systems, do far more than that.
Recovering *only* from single bit errors, is low-end server stuff.

IBM S/390 mainframes protect against memory failures by design, no
chip affect more than a single bit in the ECC code. Hence, IBM
mainframes can protect against memory chip failures, even in the
case that every bit in a chip fails. That is, the ECC logic can fix
hardware fault of a memory chip, without loss of data.

All that requires is using the cheapest available chips with ECC,
i.e. N x 1 bit memory chips. 2 bit wide can be just as cheap,
because they lose one address pin and gain one data pin. Anything
wider costs pins.