Bus reduction

Discussion in 'VHDL' started by Patrick, Jun 7, 2004.

  1. Patrick

    Patrick Guest

    Hello everybody,

    I'm very embarassed to reduce the width of a data bus from 14 to 12 bits...

    I tried this

    CONV_12 : process (RAZ,clock_dac1)
    begin
    if RAZ = '0' then
    I_12 <= (others=>'0');
    Q_12 <= (others=>'0');
    elsif (clock_dac1'event and clock_dac1='1') then
    I_12 <= I_filt(11 downto 0);
    Q_12 <= Q_filt(11 downto 0);
    end if;
    end process CONV_12;

    But like I_filt is signed, I forgot the sign in I_12 !!

    Is there any theory about this ?

    Thanks...
    Patrick, Jun 7, 2004
    #1
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  2. I do not know which packages you are using but in case you use numeric_std
    you have a function that can be used to resize objects of type unsigned and
    type signed.
    In your case where the length of the signed vector is reduced from 14 to 12
    bits the sign bits will be the same:
    I_12 <= resize(I_filt,12);

    Egbert Molenkamp

    "Patrick" <> wrote in message
    news:...
    > Hello everybody,
    >
    > I'm very embarassed to reduce the width of a data bus from 14 to 12

    bits...
    >
    > I tried this
    >
    > CONV_12 : process (RAZ,clock_dac1)
    > begin
    > if RAZ = '0' then
    > I_12 <= (others=>'0');
    > Q_12 <= (others=>'0');
    > elsif (clock_dac1'event and clock_dac1='1') then
    > I_12 <= I_filt(11 downto 0);
    > Q_12 <= Q_filt(11 downto 0);
    > end if;
    > end process CONV_12;
    >
    > But like I_filt is signed, I forgot the sign in I_12 !!
    >
    > Is there any theory about this ?
    >
    > Thanks...
    Egbert Molenkamp, Jun 7, 2004
    #2
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