c(0) <= a(0) + a(1); Found 0 definitions for operator "+"

Discussion in 'VHDL' started by matchstick86, Oct 7, 2009.

  1. matchstick86

    matchstick86

    Joined:
    Oct 2, 2009
    Messages:
    19
    I declared the library as such:
    Code:
    library IEEE;
    use IEEE.STD_LOGIC_1164.ALL;
    use IEEE.STD_LOGIC_ARITH.ALL;
    use IEEE.STD_LOGIC_UNSIGNED.ALL;
    and I want to perform the following operation

    Code:
    ...
    port (c : inout std_logic_vector (5 down to 0);
    ...
    signal a : std_logic_vector (7 downto 0);
    ...
    c(0) <= (a(0) + a(1)); c(1) <= (a(2)+a(3)); c(2) <= (a(4) + a(5)); c(3) <= (a(6) + a(7));
    ...
    
    I was trying to check behavioural syntax (for simulation) and the error I got was "Found 0 definitions for operator "+"". I've read from other sites that ieee.numeric.std cannot coexist with either ieee.std.logic.arith or ieee.std.logic.unsigned, so that should narrow the problem down a lot more. If I'm not wrong, both c and a are unsigned, so technically they should up.

    Unless I am misintepreting std_logic_vector as easily producing different values of c and a. Any help/tips?
     
    matchstick86, Oct 7, 2009
    #1
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