C++ Template Classes of Multi-Value Logic

Discussion in 'VHDL' started by Qunwei Chen, Aug 20, 2003.

  1. Qunwei Chen

    Qunwei Chen Guest

    I opened a project "C++ Template Classes of Multi-Value Logic" at
    sourceforge.net. http://hdl.sourceforge.net/. The purpose is to design a
    lightweight library for multi-value logic types including bit, logic,
    std_logic and user defined types. This library supports

    o template class mvl<T> and mvl_vector<T> with arbitrary precision.
    o user defined multi-value logic types, i.e. SUBTYPE in VHDL.
    o automatical conversion between C/C++ builtin data types and
    multi-value logic types.
    o three values boolean type (true, false and unknown).
    o arbitrary precision integer and natual.
    o bit, bit_vector.
    o logic, logic_vector.
    o std_logic, std_logic_vector.
    o "don't care" in comparison.
    o bitwise addition, substraction and multiplication to trace unknown
    value easier.

    The current release is alpha version for comments and testing. Hope it
    is useful to your projects.
    ANY COMMENTS ARE WELCOME.

    Qunwei
     
    Qunwei Chen, Aug 20, 2003
    #1
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  2. Qunwei Chen wrote:
    > I opened a project "C++ Template Classes of Multi-Value Logic" at
    > sourceforge.net. http://hdl.sourceforge.net/. The purpose is to design a
    > lightweight library for multi-value logic types including bit, logic,
    > std_logic and user defined types. This library supports
    >
    > o template class mvl<T> and mvl_vector<T> with arbitrary precision.
    > o user defined multi-value logic types, i.e. SUBTYPE in VHDL.
    > o automatical conversion between C/C++ builtin data types and
    > multi-value logic types.
    > o three values boolean type (true, false and unknown).
    > o arbitrary precision integer and natual.
    > o bit, bit_vector. o logic, logic_vector.
    > o std_logic, std_logic_vector.
    > o "don't care" in comparison.
    > o bitwise addition, substraction and multiplication to trace unknown
    > value easier.
    >
    > The current release is alpha version for comments and testing. Hope it
    > is useful to your projects.
    > ANY COMMENTS ARE WELCOME.
    >
    > Qunwei
    >


    Hello Qunwei,

    Could you briefly explain the differences between your project and the
    SystemC data types?

    Regards,
    --
    Renaud Pacalet, ENST, 46 rue Barrault 75634 Paris Cedex 13
    ###### Tel. : 01 45 81 78 08 | Fax : 01 45 80 40 36 ######
    # Fight Spam! Join EuroCAUCE: http://www.euro.cauce.org/ #
     
    Renaud Pacalet, Aug 21, 2003
    #2
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  3. Qunwei Chen

    Qunwei Chen Guest

    Some differences are listed below. Point out when I'm wrong. Thanks.

    Compare with SystemC Datatypes:
    1. Integer type
    There is no big difference with SystemC. Both support signed and unsigned
    integer. SystemC divides integer as sc_int and sc_bigint to improve speed
    as it claims. In this project, integer is not differentiated in size
    excepts the implementation has little different if the size is less or
    equal to 32. As in this project, it supports automatical conversion from
    or to C/C++ builtin data types. You can use the builtin data types to save
    memory and improve the speed.
    2. Boolean
    In this project, it supports three values boolean type (true, false and
    unknown). It is useful in logic data types. The SystemC does not have
    similar type.
    3. Logic data types
    SystemC provides only two pre-defined logic data types, bit and logic. It
    does not support '+', '-', '*', '/' and '%' directly.
    In this project, it supports user defined logic data types and provides
    three pre-defined types, bit, logic and std_logic. It supports signed and
    unsigned data, supports three-values in comparisons, supports "don't care"
    in comparisons (==, !=, >, >=, < and <=), supports '+', '-', '*', '/' and
    '%' directly, supports optional bitwise '+', '-' and '*' to help tracing
    'X' if applicable.
    4. Data conversion
    Supports automatical conversion from C/C++ data types to integer, boolean
    and logic data types and vice versa.
    Supports automatical conversion among integer, boolean and logic data types.
    Supports explicitly conversion among logic data types and can be defined
    by users.
    5. All logic data types are independent. You can use or define based on your
    needs. So, it will speed up compilation dramatically.


    Renaud Pacalet wrote:
    > Qunwei Chen wrote:
    >
    >> I opened a project "C++ Template Classes of Multi-Value Logic" at
    >> sourceforge.net. http://hdl.sourceforge.net/. The purpose is to design
    >> a lightweight library for multi-value logic types including bit,
    >> logic, std_logic and user defined types. This library supports
    >>
    >> o template class mvl<T> and mvl_vector<T> with arbitrary precision.
    >> o user defined multi-value logic types, i.e. SUBTYPE in VHDL.
    >> o automatical conversion between C/C++ builtin data types and
    >> multi-value logic types.
    >> o three values boolean type (true, false and unknown).
    >> o arbitrary precision integer and natual.
    >> o bit, bit_vector. o logic, logic_vector.
    >> o std_logic, std_logic_vector.
    >> o "don't care" in comparison.
    >> o bitwise addition, substraction and multiplication to trace unknown
    >> value easier.
    >>
    >> The current release is alpha version for comments and testing. Hope it
    >> is useful to your projects.
    >> ANY COMMENTS ARE WELCOME.
    >>
    >> Qunwei
    >>

    >
    > Hello Qunwei,
    >
    > Could you briefly explain the differences between your project and the
    > SystemC data types?
    >
    > Regards,
     
    Qunwei Chen, Aug 21, 2003
    #3
  4. Qunwei Chen

    Qunwei Chen Guest

    It's true for 64bit systems.

    Stephen Williams wrote:
    > Qunwei Chen wrote:
    >
    >> Some differences are listed below. Point out when I'm wrong. Thanks.
    >>
    >> Compare with SystemC Datatypes:
    >> 1. Integer type
    >> There is no big difference with SystemC. Both support signed and
    >> unsigned
    >> integer. SystemC divides integer as sc_int and sc_bigint to improve
    >> speed
    >> as it claims. In this project, integer is not differentiated in size
    >> excepts the implementation has little different if the size is less or
    >> equal to 32. As in this project, it supports automatical conversion
    >> from
    >> or to C/C++ builtin data types. You can use the builtin data types
    >> to save
    >> memory and improve the speed.

    >
    >
    > I presume that you mean "size is less or equal to long" because
    > there are those amongst us who have 64bit systems. (I have an
    > alpha *and* an Opteron:)
    >
     
    Qunwei Chen, Aug 22, 2003
    #4
  5. a fanQunwei Chen wrote:
    > Some differences are listed below. Point out when I'm wrong. Thanks.
    >


    Thanks. It looks interesting. My only remark concerns your boolean type:

    > 2. Boolean
    > In this project, it supports three values boolean type (true, false and
    > unknown). It is useful in logic data types. The SystemC does not have
    > similar type.


    Why not? But then raises the "if(unknown)" problem. What behaviour will
    you define for this in case boolean variable A is unknown:

    if (A)
    B = true;
    else
    B = false;

    I'm not fond of considering the boolean type as another "logic" type or
    integer type (as in C). You need a type to express conditions. Usually a
    first order logic is used where conditions are true or false. It makes
    programs understandable and deterministic. When a "logic" type is used
    to express conditions, as in Verilog with the 01XZ values, it gives some
    interesting situations:

    if(a == b)
    <dothis>;
    else
    <dothat>;

    has a different behaviour than:

    if(a != b)
    <dothat>;
    else
    <dothis>;

    You then need several versions of your equality operators (==, ===, !=,
    !==) and control structures (case, casez, casex) and you have some very
    funny definitions for conditionnal operators as "?:". I suggest that you
    have a look at "?:" definition in Verilog.

    Regards,
    --
    Renaud Pacalet, ENST, 46 rue Barrault 75634 Paris Cedex 13
    ###### Tel. : 01 45 81 78 08 | Fax : 01 45 80 40 36 ######
    # Fight Spam! Join EuroCAUCE: http://www.euro.cauce.org/ #
     
    Renaud Pacalet, Aug 22, 2003
    #5
  6. Qunwei Chen

    Qunwei Chen Guest

    The boolean will be converted automatically to C/C++ builtin bool type when it
    is used as a contional expression as the C/C++ program supports only two value
    s (true or false). The conversion between boolean and C/C++ bool is
    unknown => false
    false => false
    true => true
    Only the comparison operators (==, !=, >, >=, <, <=) will generate boolean
    type result.

    For your first case,
    if (A)
    B = true;
    else
    B = false;

    The A is converted automatically as C/C++ bool not boolean because of C/C++
    compiler. The result is false if A is unknown.

    The introduce of boolean type is for the result as in your second case. The
    behaviours might be different in using if (a==b) .. else ..., than if (a!=b)
    .... else .... It depends on whether the type of a and b supports unknown
    value. The pre-defined logic and std_logic will have unknown value in
    comparison, but the bit type has only true or false result.

    When a unknown value is in conditional expression, it usually means that there
    is something wrong in the design.

    Renaud Pacalet wrote:
    > a fanQunwei Chen wrote:
    >
    >> Some differences are listed below. Point out when I'm wrong. Thanks.
    >>

    >
    > Thanks. It looks interesting. My only remark concerns your boolean type:
    >
    >> 2. Boolean
    >> In this project, it supports three values boolean type (true, false
    >> and
    >> unknown). It is useful in logic data types. The SystemC does not have
    >> similar type.

    >
    >
    > Why not? But then raises the "if(unknown)" problem. What behaviour will
    > you define for this in case boolean variable A is unknown:
    >
    > if (A)
    > B = true;
    > else
    > B = false;
    >
    > I'm not fond of considering the boolean type as another "logic" type or
    > integer type (as in C). You need a type to express conditions. Usually a
    > first order logic is used where conditions are true or false. It makes
    > programs understandable and deterministic. When a "logic" type is used
    > to express conditions, as in Verilog with the 01XZ values, it gives some
    > interesting situations:
    >
    > if(a == b)
    > <dothis>;
    > else
    > <dothat>;
    >
    > has a different behaviour than:
    >
    > if(a != b)
    > <dothat>;
    > else
    > <dothis>;
    >
    > You then need several versions of your equality operators (==, ===, !=,
    > !==) and control structures (case, casez, casex) and you have some very
    > funny definitions for conditionnal operators as "?:". I suggest that you
    > have a look at "?:" definition in Verilog.
    >
    > Regards,
     
    Qunwei Chen, Aug 22, 2003
    #6
  7. Qunwei Chen wrote:

    > When a unknown value is in conditional expression, it usually means that
    > there is something wrong in the design.


    So you probably don't need a third value in the boolean type.

    Regards,
    --
    Renaud Pacalet, ENST, 46 rue Barrault 75634 Paris Cedex 13
    ###### Tel. : 01 45 81 78 08 | Fax : 01 45 80 40 36 ######
    # Fight Spam! Join EuroCAUCE: http://www.euro.cauce.org/ #
     
    Renaud Pacalet, Aug 22, 2003
    #7
    1. Advertising

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