S
srimks11
Hi.
I had implemented PREFETCH (PREF @R1) insn and it's perfectly
generating instructions within the assembly code. Generation of
prefetch opcode value matches with objdump generated opcode and
simulator generated opcode.
The simulator can't cross verify the content of CACHE after data is
sent from register R1 to cache.
GDB (v-6.6) doesn't have support to verify cache content.
I had build the insn on GCC(v4.3) and cross-compiled for one of the
RISC based architecture.
How can I cross-verify the cache content?
BR
Mukesh K Srivastava
I had implemented PREFETCH (PREF @R1) insn and it's perfectly
generating instructions within the assembly code. Generation of
prefetch opcode value matches with objdump generated opcode and
simulator generated opcode.
The simulator can't cross verify the content of CACHE after data is
sent from register R1 to cache.
GDB (v-6.6) doesn't have support to verify cache content.
I had build the insn on GCC(v4.3) and cross-compiled for one of the
RISC based architecture.
How can I cross-verify the cache content?
BR
Mukesh K Srivastava