Cache Memory

Discussion in 'VHDL' started by rykardu, Dec 1, 2011.

  1. rykardu

    rykardu Guest

    I'm working on a processor model written in vhdl and I'm looking for a
    model for a cache memory written in vhdl.

    The architecture of an embedded cache microarchitectureproposed by
    Tannenbaum. This cache must be of type copy back, set associative
    using two sets (2-way), with 64 positions, each set with a capacity to
    store blocks of 4 words of 16 bits.

    When a memory read is requested, the cache controller must determine
    whether it is a success or a failure and if the block stored in the
    cache is valid. If a hit, the word address must be supplied to the
    processor. If one fails, the main memory to be accessed, the cache
    should be refreshed and the bit of validity must be activated before
    the word to be supplied to the processor.

    When a write memory is requested, the cache controller must
    immediately determine whether it is a success or a failure. If a hit,
    the cache should be updated with the new word. If one fails, the cache
    must be updated with the new block and then the new word must be
    written in the cache.

    The replacement policy chooses the set of blocks that used less often.
    Only blocks that have been modified to be written back to main
    memory.

    This will need to add a bit of modification, indicating that that
    block was changed while in cache. The cache control is done by the
    microprogram. The main memory to the processor in question is 4K words
    of 16 bits.

    So, some components i have built but other not (for copy back,
    data_buffer) etc.

    I read here to try the website (www.gaisler.com) but 404.

    tks
    rykardu, Dec 1, 2011
    #1
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  2. rykardu

    Guest

    Did u get it?

    Em quinta-feira, 1 de dezembro de 2011 18h46min38s UTC-2, rykardu escreveu:
    > I'm working on a processor model written in vhdl and I'm looking for a
    >
    > model for a cache memory written in vhdl.
    >
    >
    >
    > The architecture of an embedded cache microarchitectureproposed by
    >
    > Tannenbaum. This cache must be of type copy back, set associative
    >
    > using two sets (2-way), with 64 positions, each set with a capacity to
    >
    > store blocks of 4 words of 16 bits.
    >
    >
    >
    > When a memory read is requested, the cache controller must determine
    >
    > whether it is a success or a failure and if the block stored in the
    >
    > cache is valid. If a hit, the word address must be supplied to the
    >
    > processor. If one fails, the main memory to be accessed, the cache
    >
    > should be refreshed and the bit of validity must be activated before
    >
    > the word to be supplied to the processor.
    >
    >
    >
    > When a write memory is requested, the cache controller must
    >
    > immediately determine whether it is a success or a failure. If a hit,
    >
    > the cache should be updated with the new word. If one fails, the cache
    >
    > must be updated with the new block and then the new word must be
    >
    > written in the cache.
    >
    >
    >
    > The replacement policy chooses the set of blocks that used less often.
    >
    > Only blocks that have been modified to be written back to main
    >
    > memory.
    >
    >
    >
    > This will need to add a bit of modification, indicating that that
    >
    > block was changed while in cache. The cache control is done by the
    >
    > microprogram. The main memory to the processor in question is 4K words
    >
    > of 16 bits.
    >
    >
    >
    > So, some components i have built but other not (for copy back,
    >
    > data_buffer) etc.
    >
    >
    >
    > I read here to try the website (www.gaisler.com) but 404.
    >
    >
    >
    > tks
    , Apr 26, 2014
    #2
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