cache not a ROM, inferring, xilinx

Discussion in 'VHDL' started by --MMS--, May 13, 2007.

  1. --MMS--

    --MMS-- Guest

    Hello:


    I am trying to "tell" Xilinx that the cache I designed is not a "ROM".
    When I synthetize, it keeps inferring that is a ReadOnlyMemory. What
    do I need to do to "tell" Xilinx that it is not a ROM?


    I keep getting many warning messages like...

    WARNING:Xst:737 - Found 1-bit latch for signal
    <cache<0><5>.data_20>. ..

    ...(for all the entries in my cache)...

    .......
    Found 1-bit 8-to-1 multiplexer for signal <$n5330> created at line 90.
    Found 1-bit 8-to-1 multiplexer for signal <$n5331> created at line
    90.
    .......


    At the end of the HDL synthesis summary I get:

    Summary:
    inferred 1 ROM(s).
    inferred 12 Adder/Subtractor(s).
    inferred 2 Comparator(s).
    inferred 1636 Multiplexer(s).



    Thanks thanks thanks!,
    MMS
    --MMS--, May 13, 2007
    #1
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  2. --MMS--

    Ben Jones Guest

    "--MMS--" <> wrote in message
    news:...
    > Hello:
    >
    >
    > I am trying to "tell" Xilinx that the cache I designed is not a "ROM".
    > When I synthetize, it keeps inferring that is a ReadOnlyMemory. What
    > do I need to do to "tell" Xilinx that it is not a ROM?
    > I keep getting many warning messages like...
    > WARNING:Xst:737 - Found 1-bit latch for signal
    > <cache<0><5>.data_20>. ..
    > ..(for all the entries in my cache)...


    Then it's inferring latches, not a ROM. (I notice that there's a ROM in the
    synthesis summary, but that's probably unrelated.) Those multiplexors are
    probably connected to the latch outputs, and are implementing the read data
    output path for your cache array.

    You probably need to re-phrase your code to remove these latches and thus
    allow the software to implement your cache array as RAM instead. Search this
    newsgroup for "latch" or read the software manuals to find out what's going
    wrong and how to fix it.

    -Ben-
    Ben Jones, May 14, 2007
    #2
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  3. --MMS--

    --MMS-- Guest

    OMG......

    Below is the code. There must be an angel out there...

    ---------------------------------------------------------------------------
    library IEEE;
    use IEEE.STD_LOGIC_1164.ALL;
    use IEEE.STD_LOGIC_ARITH.ALL;
    use IEEE.STD_LOGIC_UNSIGNED.ALL;
    USE work.types.ALL;


    entity cachee is
    Port (
    Write_enable : in std_logic;
    Clock : in std_logic;
    databus : inout std_logic_vector(31 downto 0);
    Address : inout std_logic_vector(18 downto 0);
    chip_select : inout std_logic
    );
    end cachee;


    architecture Behavioral of cachee is

    SUBTYPE ways IS INTEGER RANGE 0 TO 1;
    SUBTYPE sets IS INTEGER RANGE 0 TO 2**13-1;
    SUBTYPE tags IS std_logic_vector (4 DOWNTO 0);


    TYPE entry IS RECORD
    -- valid : BOOLEAN;
    tag : tags;
    data: std_logic_vector(31 downto 0);
    END RECORD;


    TYPE lru_type IS ARRAY (sets) OF ways;

    TYPE eachCache IS ARRAY (sets) OF entry;

    Type elCache is array (INTEGER RANGE 0 TO 1) of eachCache;

    TYPE ww IS ARRAY(ways) OF ways;

    Signal cache : elCache :=
    (
    others =>
    (
    others =>
    (
    tag => (others => '0'),
    data => (others => '0')
    )
    )
    );



    Signal lru : lru_type :=
    (
    others =>
    (
    others =>
    (
    tag => (others => '0'),
    data => (others => '0')
    )
    )
    );



    begin

    unProceso : Process(Clock, chip_select)

    VARIABLE s : sets;
    VARIABLE hit : BOOLEAN;
    VARIABLE w, free : ways;
    VARIABLE nw : ww := (1, 0);


    ALIAS ss : std_logic_vector (12 DOWNTO 0) IS Address(13 DOWNTO 1);

    ALIAS tag_value : tags IS Address(18 DOWNTO 14);


    begin

    if (Clock'event and Clock = '0') then

    s := bits_to_int(To_bitvector(ss));
    hit := FALSE;


    FOR i IN ways LOOP
    IF cache(i)(s).tag = tag_value then
    --cache(i)(s).valid THEN
    hit := TRUE;
    w := i;
    END IF;
    END LOOP;


    --a hit
    IF hit THEN
    lru (s) <= nw (w);


    --write data in cache and memory
    if (Write_enable = '1') then
    databus <= cache(w)(s).data ;


    --pass data to cache
    else

    cache(w)(s).data <= databus after 10 ns;
    cache(w)(s).tag <= tag_value;
    end if;


    --a miss
    else
    --find least recently used
    free := lru (s);
    lru (s) <= nw (lru (s));

    --write data in cache and memory
    if (Write_enable = '1') then
    databus <= cache(w)(s).data ;

    else


    --read from memory and pass it to cache
    cache(free)(s).data <= databus after 10 ns;
    cache(free)(s).tag <= tag_value;

    end if;

    end if;

    end if;
    end process;
    end Behavioral;

    --------------------------------------------------------------------
    ---------------------------------------------------------------------
    On May 14, 4:18 am, "Ben Jones" <> wrote:
    >
    > Then it's inferring latches, not a ROM. (I notice that there's a ROM in the
    > synthesis summary, but that's probably unrelated.) Those multiplexors are
    > probably connected to the latch outputs, and are implementing the read data
    > output path for your cache array.
    >
    > You probably need to re-phrase your code to remove these latches and thus
    > allow the software to implement your cache array as RAM instead. Search this
    > newsgroup for "latch" or read the software manuals to find out what's going
    > wrong and how to fix it.
    >
    > -Ben-
    --MMS--, May 15, 2007
    #3
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