Cadence compiler basics

Discussion in 'VHDL' started by PC, Jun 18, 2008.

  1. PC

    PC Guest

    Hi all,

    I have a very very basic problem with the cadence VHDL compiler
    For example

    signal test : std_logic_vector( 15 downto 0);
    begin

    test<="1111111111111111" ; works fine
    test<=x"ffff"; gives an error expecting an expression of type
    STD_LOGIC_VECTOR 87[8.3] 93[8.4] why ?

    thanks in advance
    PC
    PC, Jun 18, 2008
    #1
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  2. PC

    HT-Lab Guest

    "PC" <> wrote in message
    news:...
    > Hi all,
    >
    > I have a very very basic problem with the cadence VHDL compiler
    > For example
    >
    > signal test : std_logic_vector( 15 downto 0);
    > begin
    >
    > test<="1111111111111111" ; works fine
    > test<=x"ffff"; gives an error expecting an expression of type
    > STD_LOGIC_VECTOR 87[8.3] 93[8.4] why ?


    The code is fine, try compiling with the VHDL93 standard,

    Hans
    www.ht-lab.com


    >
    > thanks in advance
    > PC
    HT-Lab, Jun 18, 2008
    #2
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