cadence NCVHDL simulation

Discussion in 'VHDL' started by Lily, Apr 27, 2004.

  1. Lily

    Lily Guest

    Hi,

    I've got problem with my ALU testbench. the testbench works fine when
    i simulate and extract but when i try to view the waveform it is
    complaining as below

    ncsim> run

    Error! TEXTIO error
    LINE of length 0 on READ of type CHARACTER

    below is my full testbench program. could anybody out there help me
    pls ?

    thanks a lot.





    use ieee.std_logic_1164.all;
    use std.textio.all;
    use work.all;
    use ieee.numeric_std.all;
    use ieee.std_logic_textio.all;

    library std;



    entity alu_testbench is
    end alu_testbench;

    architecture test_alu of alu_testbench is
    component alu_testbench
    generic(
    OPERAND_WIDTH : integer :=8);
    port(
    opcode : in std_logic_vector(3 downto 0);
    operand1 : in std_logic_vector(OPERAND_WIDTH-1 downto 0);
    operand2 : in std_logic_vector(OPERAND_WIDTH-1 downto 0);
    result : out std_logic_vector(OPERAND_WIDTH-1 downto 0)
    );
    end component;


    constant clk_period: time := 5 ns;
    constant OPERAND_WIDTH : integer := 8;

    -- declare math opcode constants
    constant ADD : std_logic_vector(3 downto 0) := "0000";
    constant SUB : std_logic_vector(3 downto 0) := "0010";
    constant INC : std_logic_vector(3 downto 0) := "0001";
    constant CMP : std_logic_vector(3 downto 0) := "0011";

    -- declare logical opcode constants
    constant opAND : std_logic_vector(3 downto 0) := "1100";
    constant opOR : std_logic_vector(3 downto 0) := "1101";
    constant opXOR : std_logic_vector(3 downto 0) := "1110";
    constant opCPL : std_logic_vector(3 downto 0) := "1111";


    signal clk : std_logic;
    signal rst : std_logic;
    signal opcode : std_logic_vector(3 downto 0);
    signal operand1 : std_logic_vector(OPERAND_WIDTH-1 downto 0);
    signal operand2 : std_logic_vector(OPERAND_WIDTH-1 downto 0);
    signal done : std_logic := '0';
    signal result : std_logic_vector(OPERAND_WIDTH-1 downto 0);



    for t1 : alu_testbench use entity work.alu_structure;


    begin -- behavior
    t1 : alu_testbench


    port map (
    opcode => opcode,
    operand1 => operand1,
    operand2 => operand2,
    result => result);

    -- the clock
    clk <= '0' when rst = '1'
    else not clk after clk_period when (done = '0')
    else '0';

    -- printstatus process

    Printstatus : process

    file infile : text is in "input.txt";
    --file outfile : text is out "output.txt";
    variable aluinput : std_logic_vector(19 downto 0) :=
    "00000000000000000000";
    variable buff : line;

    begin
    while not (endfile(infile)) loop
    readline(infile, buff);
    read(buff,aluinput);

    operand1(0) <= aluinput(0);
    operand1(1) <= aluinput(1);
    operand1(2) <= aluinput(2);
    operand1(3) <= aluinput(3);
    operand1(4) <= aluinput(4);
    operand1(5) <= aluinput(5);
    operand1(6) <= aluinput(6);
    operand1(7) <= aluinput(7);

    operand2(0) <= aluinput(8);
    operand2(1) <= aluinput(9);
    operand2(2) <= aluinput(10);
    operand2(3) <= aluinput(11);
    operand2(4) <= aluinput(12);
    operand2(5) <= aluinput(13);
    operand2(6) <= aluinput(14);
    operand2(7) <= aluinput(15);

    opcode(0) <= aluinput(16);
    opcode(1) <= aluinput(17);
    opcode(2) <= aluinput(18);
    opcode(3) <= aluinput(19);



    end loop;
    wait;
    end process Printstatus;

    -- verification process
    verify : process(rst, clk)
    begin
    if clk'event and clk = '0' then
    if now > 0 ps then
    if opcode(3) = '0' then -- arithmetic opcodes
    case opcode(3 downto 0) is
    when ADD =>
    assert(result = std_logic_vector(unsigned(operand1) +
    unsigned(operand2)))
    report "Incorrect result adding"
    severity error;
    when SUB =>
    assert(result = std_logic_vector(unsigned(operand1) -
    unsigned(operand2)))
    report "Incorrect result subtracting"
    severity error;
    --when INC =>
    --assert(result = std_logic_vector(unsigned(operand1) +
    )))
    --report "Incorrect result increment"
    --severity error;


    when others =>
    assert(false)
    report "simulation error: invalid math opcode!"
    severity failure;
    end case;
    else -- logic opcodes
    case opcode(3 downto 0) is
    when opAND =>
    assert(result = (operand1 and operand2))
    report "Incorrect result ANDing"
    severity error;
    when opOR =>
    assert(result = (operand1 or operand2))
    report "Incorrect result ORing"
    severity error;
    when opXOR =>
    assert(result = (operand1 xor operand2))
    report "Incorrect result XORing"
    severity error;
    when opCPL =>
    assert(result = (not operand2))
    report "Incorrect result Complement(operand2)"
    severity error;
    when others =>
    assert(false)
    report "simulation error: invalid logic opcode!"
    severity failure;
    end case;
    end if;
    end if;
    end if;
    end process verify;
    -- *** End Test Bench - User Defined Section ***



    end test_alu;
    Lily, Apr 27, 2004
    #1
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  2. Lily wrote:
    >
    > I've got problem with my ALU testbench. the testbench works fine when
    > i simulate and extract but when i try to view the waveform it is
    > complaining as below
    >
    > ncsim> run
    >
    > Error! TEXTIO error
    > LINE of length 0 on READ of type CHARACTER


    It looks like it will read the entire file
    in zero sim time. Maybe you want to synch the reads?
    Consider using a constant array instead of a file.

    The clock is stick at 'U'. Needs an init.

    Consider using a '93 file declaration:
    file infile : text open read_mode is "input.txt";

    -- Mike Treseler
    Mike Treseler, Apr 28, 2004
    #2
    1. Advertising

  3. Lily

    Lily Guest

    Helo,

    Thanks for your help. Do you mind to explain what do you mean by
    'synch the reads' ? I am beginner to vhdl/vlsi, i still have lots to
    learn :) Could you please give the vhdl code example.

    i have declare the clock process as below but still it is not working.
    do you know what might be wrong ?

    clk : process
    begin -- process clk
    clock <= '0', '1' after 5 ns;
    wait for 10 ns;
    end process clk;

    Lily

    (Mike Treseler) wrote in message news:<>...
    > Lily wrote:
    > >
    > > I've got problem with my ALU testbench. the testbench works fine when
    > > i simulate and extract but when i try to view the waveform it is
    > > complaining as below
    > >
    > > ncsim> run
    > >
    > > Error! TEXTIO error
    > > LINE of length 0 on READ of type CHARACTER

    >
    > It looks like it will read the entire file
    > in zero sim time. Maybe you want to synch the reads?
    > Consider using a constant array instead of a file.
    >
    > The clock is stick at 'U'. Needs an init.
    >
    > Consider using a '93 file declaration:
    > file infile : text open read_mode is "input.txt";
    >
    > -- Mike Treseler
    Lily, Apr 28, 2004
    #3
  4. Lily

    paris Guest

    "Lily" <> escribió en el mensaje
    news:...
    > Helo,
    >
    > Thanks for your help. Do you mind to explain what do you mean by
    > 'synch the reads' ? I am beginner to vhdl/vlsi, i still have lots to
    > learn :) Could you please give the vhdl code example.
    >


    "sync the reads" means that you should put a "wait" inside the "loop" that
    reads the file, otherwise it reads the whole file in t=0 as Mike said.
    use something like "wait until rising_edge(clk);" inside the loop, or you
    could use something like:

    process(clk, rstn)
    begin
    if rstn = '0' then
    something;
    elsif rising_edge(clk) then
    if not endfile(file) then
    readline();
    read();
    assign_signals;
    end if;
    end if;
    end process;

    > i have declare the clock process as below but still it is not working.
    > do you know what might be wrong ?
    >
    > clk : process
    > begin -- process clk
    > clock <= '0', '1' after 5 ns;
    > wait for 10 ns;
    > end process clk;
    >
    > Lily
    >


    try:

    clk <= not clk after clk_period;

    clk should be initialised to some value in its signal declaration

    also, rst has no default value and it's not assigned either in your original
    code
    rst is not used in your verification process, though it is in the sensivity
    list

    you could also use:

    opcode(3 downto 0) <= aluinput(19 downto 16);
    operand2 <= aluinput(15 downto 8);
    operand1 <= aluinput(7 downto 0);

    for alu_testbench, when you instantiate it, consider using "generic map"
    even if it is to assign it to the already default value
    besides it's probably called another name cause your test bench's entity is
    called "alu_testbench" and then you have a component called the same name
    inside it's architecture, i dont know if it worked that way, but i wouldnt
    use the same name.





    > (Mike Treseler) wrote in message

    news:<>...
    > > Lily wrote:
    > > >
    > > > I've got problem with my ALU testbench. the testbench works fine when
    > > > i simulate and extract but when i try to view the waveform it is
    > > > complaining as below
    > > >
    > > > ncsim> run
    > > >
    > > > Error! TEXTIO error
    > > > LINE of length 0 on READ of type CHARACTER

    > >
    > > It looks like it will read the entire file
    > > in zero sim time. Maybe you want to synch the reads?
    > > Consider using a constant array instead of a file.
    > >
    > > The clock is stick at 'U'. Needs an init.
    > >
    > > Consider using a '93 file declaration:
    > > file infile : text open read_mode is "input.txt";
    > >
    > > -- Mike Treseler
    paris, Apr 28, 2004
    #4
  5. Lily

    Lily Guest

    thank you for your help
    i've got the simulation running... :)

    lily

    "paris" <> wrote in message news:<c6onlr$jbo$>...
    > "Lily" <> escribió en el mensaje
    > news:...
    > > Helo,
    > >
    > > Thanks for your help. Do you mind to explain what do you mean by
    > > 'synch the reads' ? I am beginner to vhdl/vlsi, i still have lots to
    > > learn :) Could you please give the vhdl code example.
    > >

    >
    > "sync the reads" means that you should put a "wait" inside the "loop" that
    > reads the file, otherwise it reads the whole file in t=0 as Mike said.
    > use something like "wait until rising_edge(clk);" inside the loop, or you
    > could use something like:
    >
    > process(clk, rstn)
    > begin
    > if rstn = '0' then
    > something;
    > elsif rising_edge(clk) then
    > if not endfile(file) then
    > readline();
    > read();
    > assign_signals;
    > end if;
    > end if;
    > end process;
    >
    > > i have declare the clock process as below but still it is not working.
    > > do you know what might be wrong ?
    > >
    > > clk : process
    > > begin -- process clk
    > > clock <= '0', '1' after 5 ns;
    > > wait for 10 ns;
    > > end process clk;
    > >
    > > Lily
    > >

    >
    > try:
    >
    > clk <= not clk after clk_period;
    >
    > clk should be initialised to some value in its signal declaration
    >
    > also, rst has no default value and it's not assigned either in your original
    > code
    > rst is not used in your verification process, though it is in the sensivity
    > list
    >
    > you could also use:
    >
    > opcode(3 downto 0) <= aluinput(19 downto 16);
    > operand2 <= aluinput(15 downto 8);
    > operand1 <= aluinput(7 downto 0);
    >
    > for alu_testbench, when you instantiate it, consider using "generic map"
    > even if it is to assign it to the already default value
    > besides it's probably called another name cause your test bench's entity is
    > called "alu_testbench" and then you have a component called the same name
    > inside it's architecture, i dont know if it worked that way, but i wouldnt
    > use the same name.
    >
    >
    >
    >
    >
    > > (Mike Treseler) wrote in message

    > news:<>...
    > > > Lily wrote:
    > > > >
    > > > > I've got problem with my ALU testbench. the testbench works fine when
    > > > > i simulate and extract but when i try to view the waveform it is
    > > > > complaining as below
    > > > >
    > > > > ncsim> run
    > > > >
    > > > > Error! TEXTIO error
    > > > > LINE of length 0 on READ of type CHARACTER
    > > >
    > > > It looks like it will read the entire file
    > > > in zero sim time. Maybe you want to synch the reads?
    > > > Consider using a constant array instead of a file.
    > > >
    > > > The clock is stick at 'U'. Needs an init.
    > > >
    > > > Consider using a '93 file declaration:
    > > > file infile : text open read_mode is "input.txt";
    > > >
    > > > -- Mike Treseler
    Lily, May 2, 2004
    #5
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