Cambridge U.K and the use of verilog

[Jezmo]

Does anyone know why there is a sudden increase in the number of
cambridge companies asking for new hires who work in verilog ? I hope
it isn't down to an increase in the number of American CTOs who don't
understand VHDL.

 

[Tricky]

Does anyone know why there is a sudden increase in the number of
cambridge companies asking for new hires who work in verilog ? I hope
it isn't down to an increase in the number of American CTOs who don't
understand VHDL.

Is it not just a recruitment drive by the local ASIC producers, whom I
always understood to be more common verilog users than VHDL?

 

[Jezmo]

Is it not just a recruitment drive by the local ASIC producers, whom I
always understood to be more common verilog users than VHDL?

You may well be right, I had a strange call from a recruitment firm
asking me if I wanted to do processor design in VHDL and then started
asking me about had I done verification using verilog and
systemverilog, sometimes it really makes you wonder if they understand
what the hell they are talking about.

 

[Thomas Stanka]

You may well be right, I had a strange call from a recruitment firm
asking me if I wanted to do processor design in VHDL and then started
asking me about had I done verification using verilog and
systemverilog, sometimes it really makes you wonder if they understand
what the hell they are talking about.

I see a trend to design RTL in VHDL and build testbenches in SV.
Another trend is usage of IP in whatever language you get the IP,
resulting in mixed language designs.
So you need designers with good skills in VHDL but also able to
understand a bit Verilog (SV, C,...).

bye Thomas

 

[Jezmo]

I see a trend to design RTL in VHDL and build testbenches in SV.
Another trend is usage of IP in whatever language you get the IP,
resulting in mixed language designs.
So you need designers with good skills in VHDL but also able to
understand a bit Verilog (SV, C,...).

bye Thomas

Well it just so happens that I am working on a JESD204B interface
which may need to be written in verilog depending on what people want,
so that will be fun, possibly.