CAn any one help me in understanding these 3 lines in code from PLL??

Discussion in 'VHDL' started by maheshkumar0459, Jul 6, 2011.

  1. maheshkumar0459

    maheshkumar0459

    Joined:
    Jul 5, 2011
    Messages:
    5
    1)part0 <= (others => '0'); // What result can be achieved from above??//

    2)part7 <= -(input1_buf); //Wt does this meant for??//

    3)out_temp <= part0+(part1(14 downto 0)&'0')+
    (part2(13 downto 0)&"00")+
    (part3(12 downto 0)&"000")+
    (part4(11 downto 0)&"0000")+
    (part5(10 downto 0)&"00000")+
    (part6(9 downto 0)&"000000")+
    (part7(8 downto 0)&"0000000"); //Why shud add these all??//


    Thanks in advance from Mahesh
    maheshkumar0459, Jul 6, 2011
    #1
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