can any one help me in VHDL codes plz

Discussion in 'VHDL' started by majmoat_ensan, Jul 6, 2011.

  1. hi all,

    really i want a help in these 2 problems :

    1)
    I want a structural VHDL code of 1 to 16 Demultiplexers. with an
    active low Enable signal using 1 to 2 Demultiplexer. [ use Generate
    statement]

    __________________________________________________ ____________
    2)
    Also I need a structure and behavior VHDL code of 5-bits binary
    counter with a synchronous load signal to preset the counter to a
    specific initial state. the output of the counter ( Q0 to Q4) are
    connected to a binary decoder that shows the state of the counter.
     
    majmoat_ensan, Jul 6, 2011
    #1
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  2. majmoat_ensan

    eliascm

    Joined:
    Jan 30, 2009
    Messages:
    42
    Help with Code

    You don't want help, you want someone to do your assignment for you. If you won't even make an effort to do the work on your own, it is unlikely that anyone will be inclined to help you. More importantly, you will learn little or nothing about VHDL.
     
    eliascm, Jul 6, 2011
    #2
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  3. majmoat_ensan

    Tricky Guest

    Wheres the problem? Looks like a set of exercises you havent started
    yet.

    Or is the problem you're too lazy to do it yourself?

    On Jul 6, 8:51 am, majmoat_ensan <>
    wrote:
    > hi all,
    >
    > really i want a help in these 2 problems :
    >
    > 1)
    > I want a structural VHDL code of 1 to 16 Demultiplexers. with an
    > active low Enable signal using 1 to 2 Demultiplexer. [ use Generate
    > statement]
    >
    > __________________________________________________ ____________
    > 2)
    > Also I need a structure and behavior VHDL code of 5-bits binary
    > counter with a synchronous load signal to preset the counter to a
    > specific initial state. the output of the counter ( Q0 to Q4) are
    > connected to a binary decoder that shows the state of the counter.
     
    Tricky, Jul 6, 2011
    #3
  4. majmoat_ensan

    KJ Guest

    On Jul 6, 3:51 am, majmoat_ensan <>
    wrote:
    > hi all,
    >
    > really i want a help in these 2 problems :
    >
    > 1)
    > I want a structural VHDL code of 1 to 16 Demultiplexers. with an
    > active low Enable signal using 1 to 2 Demultiplexer. [ use Generate
    > statement]
    >
    > __________________________________________________ ____________
    > 2)
    > Also I need a structure and behavior VHDL code of 5-bits binary
    > counter with a synchronous load signal to preset the counter to a
    > specific initial state. the output of the counter ( Q0 to Q4) are
    > connected to a binary decoder that shows the state of the counter.


    What have you tried so far?
    What were the results?
    If you're just fishing for homework help, try a different pond where
    somebody must be silly enough to bite.

    KJ
     
    KJ, Jul 7, 2011
    #4
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