can I do such a simplest counter in VHDL?

Discussion in 'VHDL' started by walala, Sep 14, 2003.

  1. walala

    walala Guest

    Dear all,

    The following is a fragment of my 6 bit counter, from 0 to 63 then wrap
    back, going on and on, ...

    if count = B"111111" then
    count <= B"000000";
    else
    count <= count + '1';
    end if;

    where count is defiend as STD_LOGIC_VECTOR(5 downto 0)

    Since resource is very precious, can I eliminate the "if" statement and rely
    on the automatic overflow property when "count" increment from 63 to 64?

    That's to say, if I just put,

    count <= count + '1';

    and the count will automatic overflow to 0 from 63, because it is a 6 bit
    counter...

    The above is done in a clocked synchronous manner, ... it seems ok with
    MODELSIM simulation, but is there any hidden problem when implemented in
    hardware ?

    Thanks for pointing out any issue for me!

    -Walala
     
    walala, Sep 14, 2003
    #1
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  2. walala

    VhdlCohen Guest

    >
    >The following is a fragment of my 6 bit counter, from 0 to 63 then wrap
    >back, going on and on, ...
    >
    > if count = B"111111" then
    > count <= B"000000";
    > else
    > count <= count + '1';
    > end if;
    >
    >where count is defiend as STD_LOGIC_VECTOR(5 downto 0)
    >
    >Since resource is very precious, can I eliminate the "if" statement and rely
    >on the automatic overflow property when "count" increment from 63 to 64?
    >
    >That's to say, if I just put,
    >
    > count <= count + '1';
    >
    >and the count will automatic overflow to 0 from 63, because it is a 6 bit
    >counter...
    >
    >The above is done in a clocked synchronous manner, ... it seems ok with
    >MODELSIM simulation, but is there any hidden problem when implemented in
    >hardware ?
    >
    >Thanks for pointing out any issue for me!
    >
    >-Walala


    You're OK for synthesis
    Ben
    ----------------------------------------------------------------------------
    Ben Cohen Publisher, Trainer, Consultant (310) 721-4830
    http://www.vhdlcohen.com/
    Author of following textbooks:
    * Using PSL/SUGAR with Verilog and VHDL
    Guide to Property Specification Language for ABV, 2003 isbn 0-9705394-4-4
    * Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn
    0-9705394-2-8
    * Component Design by Example ", 2001 isbn 0-9705394-0-1
    * VHDL Coding Styles and Methodologies, 2nd Edition, 1999 isbn 0-7923-8474-1
    * VHDL Answers to Frequently Asked Questions, 2nd Edition, isbn 0-7923-8115
    ------------------------------------------------------------------------------
     
    VhdlCohen, Sep 14, 2003
    #2
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  3. walala

    walala Guest

    Dear Cohen,

    Thank you for your answer.

    So the counter made super easy! And the post-synthesis and post-layout
    verification won't have any problem, right?

    Thanks

    -Walala


    "VhdlCohen" <> wrote in message
    news:...
    > >
    > >The following is a fragment of my 6 bit counter, from 0 to 63 then wrap
    > >back, going on and on, ...
    > >
    > > if count = B"111111" then
    > > count <= B"000000";
    > > else
    > > count <= count + '1';
    > > end if;
    > >
    > >where count is defiend as STD_LOGIC_VECTOR(5 downto 0)
    > >
    > >Since resource is very precious, can I eliminate the "if" statement and

    rely
    > >on the automatic overflow property when "count" increment from 63 to 64?
    > >
    > >That's to say, if I just put,
    > >
    > > count <= count + '1';
    > >
    > >and the count will automatic overflow to 0 from 63, because it is a 6 bit
    > >counter...
    > >
    > >The above is done in a clocked synchronous manner, ... it seems ok with
    > >MODELSIM simulation, but is there any hidden problem when implemented in
    > >hardware ?
    > >
    > >Thanks for pointing out any issue for me!
    > >
    > >-Walala

    >
    > You're OK for synthesis
    > Ben
    > --------------------------------------------------------------------------

    --
    > Ben Cohen Publisher, Trainer, Consultant (310) 721-4830
    > http://www.vhdlcohen.com/
    > Author of following textbooks:
    > * Using PSL/SUGAR with Verilog and VHDL
    > Guide to Property Specification Language for ABV, 2003 isbn

    0-9705394-4-4
    > * Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn
    > 0-9705394-2-8
    > * Component Design by Example ", 2001 isbn 0-9705394-0-1
    > * VHDL Coding Styles and Methodologies, 2nd Edition, 1999 isbn

    0-7923-8474-1
    > * VHDL Answers to Frequently Asked Questions, 2nd Edition, isbn

    0-7923-8115
    > --------------------------------------------------------------------------

    ----
    >
    >
     
    walala, Sep 14, 2003
    #3
  4. walala

    VhdlCohen Guest

    >
    >So the counter made super easy! And the post-synthesis and post-layout
    >verification won't have any problem, right?
    >


    Correct. Below is an example form my Real CHip Design book that compiles OK
    in Synplify. Your compiler may not have the NUMERIC_UNSIGNED package
    precompiled into library IEEE. You may need to do that yourself.
    Alternatively, you may us the
    Numeric package, and do type conversions on your signals.
    Ben


    library ieee;
    use ieee.std_logic_1164.all;
    use ieee.NUMERIC_UNSIGNED.all;
    entity counterun is
    generic (
    SIZE : natural := 8);

    port (
    count_out : out std_logic_vector(SIZE -1 downto 0); -- counter output
    data_in : in std_logic_vector(SIZE - 1 downto 0); -- data to load
    ld_enb : in std_logic; -- parallel load enable, active hi
    count_enb : in std_logic; -- count enable, active hig
    rst_n : in std_logic; -- reset, active hi
    clk : in std_logic -- system clock
    );
    end entity counterun;

    architecture rtl of counterun is
    -- Local signal because it has to be read internally
    -- unsigned type used because of "+" operation needed
    signal count : std_logic_vector(SIZE - 1 downto 0); -- counter reg
    begin -- architecture rtl

    Counter_proc : process (clk, rst_n) is
    begin -- process COunter_proc
    if (rst_n = '0') then
    count <= (others => '0');
    elsif (clk'event and Clk = '1') then
    if (ld_enb = '1') then
    count <= data_in;
    elsif (count_enb = '1') then
    count <= count + 1;
    end if;
    end if;
    end process Counter_proc;

    -- Assignment to output
    count_out <= count;
    end architecture rtl;

    ----------------------------------------------------------------------------
    Ben Cohen Publisher, Trainer, Consultant (310) 721-4830
    http://www.vhdlcohen.com/
    Author of following textbooks:
    * Using PSL/SUGAR with Verilog and VHDL
    Guide to Property Specification Language for ABV, 2003 isbn 0-9705394-4-4
    * Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn
    0-9705394-2-8
    * Component Design by Example ", 2001 isbn 0-9705394-0-1
    * VHDL Coding Styles and Methodologies, 2nd Edition, 1999 isbn 0-7923-8474-1
    * VHDL Answers to Frequently Asked Questions, 2nd Edition, isbn 0-7923-8115
    ------------------------------------------------------------------------------
     
    VhdlCohen, Sep 14, 2003
    #4
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