Can I include include a constant in a constant array?

[Fredxx]

Example

type word_type is array (0 to 1) of std_logic_vector(7 downto 0);
constant height : word_type := (x"04", x"05");

and I would like to place this constant in

type Con_Array_type is array (0 to size - 1) of std_logic_vector(7 downto
0);
constant Con_Array : Con_Array_type := (
x"00", x"01",
x"02", x"03",
height[1], height[0],
x"06", x"07"
);

Is this possible? If so where am I going wrong?

 

[Fredxx]

type word_type is array (0 to 1) of std_logic_vector(7 downto 0);
constant height : word_type := (x"04", x"05");

and I would like to place this constant in

type Con_Array_type is array (0 to size - 1) of std_logic_vector(7 downto
0);
constant Con_Array : Con_Array_type := (
x"00", x"01",
x"02", x"03",
height[1], height[0],
x"06", x"07"
);

Is this possible?

I think so.

If so where am I going wrong?

Square brackets for VHDL array subscripts?

What kind of error message do you get?
--
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<feeling_embarrassed>
Thank you very kindly for your prompt reply. It was indeed the square
brackets as I was porting some code from "C"!!!
Now all working.
</feeling_embarrassed>

 

[Mark McDougall]

<feeling_embarrassed>
Thank you very kindly for your prompt reply. It was indeed the square
brackets as I was porting some code from "C"!!!
Now all working.
</feeling_embarrassed>

LOL!

Wait 'til you're debugging a mixed-language design, with VHDL and Verilog,
which includes a soft-core processor running C-code! You get some
interesting syntax errors there!

Regards,

 

[Martin Thompson]

LOL!

Wait 'til you're debugging a mixed-language design, with VHDL and Verilog,
which includes a soft-core processor running C-code! You get some
interesting syntax errors there!

Then try and compare your results with the Matlab simulation indexing
from 1 rather than 0 as well for yet more debugging fun

Cheers,
Martin