can i increase da simulation speed of design

Discussion in 'VHDL' started by anupam, Sep 2, 2004.

  1. anupam

    anupam Guest

    Hi everybody,
    can I increase the simulation speed of my designs . I am using ModelSim
    Altera version 5.8c

    Thanx in advance.

    Anupam
     
    anupam, Sep 2, 2004
    #1
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  2. anupam

    ALuPin Guest

    Of course it depends on the design.
    What kind of design do you have ?

    "anupam" <> wrote in message news:<>...
    > Hi everybody,
    > can I increase the simulation speed of my designs . I am using ModelSim
    > Altera version 5.8c
    >
    > Thanx in advance.
    >
    > Anupam
     
    ALuPin, Sep 2, 2004
    #2
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  3. anupam

    anupam Guest

    I am working with VHDL code for multichannel HDLC.
    Regards,
    Anupam
     
    anupam, Sep 3, 2004
    #3
  4. anupam wrote:
    > can I increase the simulation speed of my designs . I am using ModelSim
    > Altera version 5.8c I am working with VHDL code for multichannel HDLC.


    Simulation of source code runs about
    ten times faster than simulation of
    a netlist.

    -- Mike Treseler
     
    Mike Treseler, Sep 3, 2004
    #4
  5. On Fri, 03 Sep 2004 06:32:15 -0700, Mike Treseler
    <> wrote:

    >anupam wrote:
    >> can I increase the simulation speed of my designs . I am using ModelSim
    >> Altera version 5.8c I am working with VHDL code for multichannel HDLC.

    >
    >Simulation of source code runs about
    >ten times faster than simulation of
    >a netlist.


    My source code often has lots of low level library primitives (e.g.
    from Xilinx's Unisim library) and these are very slow. Replacing them
    with behavioural models (with no timing checks, etc.) typically
    improves simulation speed by 2-3 times.

    The basic rule is: the higher the level of abstraction, the faster the
    simulation.

    Regards,
    Allan
     
    Allan Herriman, Sep 3, 2004
    #5
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