can I specify a time-varying clock?

E

edick

I need to simulate a circuit that uses a clock that varies over time,
e.g. starts out nominal at, say 80 MHz, and then, gradually slows down
to 2% below that center frequency, then gradually increases in
frequency to 2% above that frequency, then comes back to the nominal
80 MHz rate in a period of, say, 1/60 second.

Imagine using a sweep signal generator to produce such a cycle.

Is there a cool way to specify such a thing in VHDL?

Thanks!
 
C

cristian_ciressan

You probably need this feature for a spread-spectrum clocking
simulation.
Here is another example of clock you may consider using:

use generics to provide the values for:

SSC_ENABLE : boolean := FALSE;
SSC_PERIOD : real := 33333000.0; -- expressed in [ps] (this would be
1/60 expressed in [ps] in your case)

use the following procedure to compute the <Iterations> and <Delta>
parameters:

procedure ComputeIterationsAndDelta(variable Iterations: out integer;
variable Delta: out real) is
variable T_start : real; -- start period
variable T_stop : real; -- stop period
variable Iterations_real : real;
begin

-- replace values of T_start and T_stop as required by you
freq. modulation specifications ...

-- T_start = 4000 ps; (12500 ps in your case)
-- T_stop = T_start + Iterations*Delta = 4020 ps; because it is
modulated 0.5% (2% in your case 12750 ps)
-- where <Iterations> is to be determined and <Delta > is also to be
determined
-- at this point we know <Iterations*Delta> = 20 ps! (250 ps for you)

-- we also know that :
-- T_start + (T_start + Delta) + ((T_start + 2*Delta) + ....
+ ((T_start + Iterations*Delta) = SSC_PERIOD/2
-- or: 2*(Iterations + 1)*T_start + Iterations*(Iterations + 1)*Delta
= SSC_PERIOD
-- or: 8020[ps]*(Iterations + 1) = SSC_PERIOD

-- !!!!! You should change accordingly the values below)

Iterations_real := (SSC_PERIOD - 8020.0) / (8020.0);
Delta := 20.0e-12 / Iterations_real;

Iterations := integer(Iterations_real);
end procedure;

and the code to have either a SSC modulation or a normal clock.
The code is very simple.

SSC_GENERATE: if (SSC_ENABLE = TRUE) generate

-- Generate SSC Reference Clock input (250MHz)
process
variable Iterations : integer;
variable Delta : real;
variable it : integer;
variable sign : integer;
variable my_time : time;
begin
ComputeIterationsAndDelta(Iterations, Delta);

it := 0;
sign := +1;

loop
my_time := REFCLK_PERIOD + (real(it) * Delta)*1 sec;

refclk_n_r <= '1';
wait for my_time/2;
refclk_n_r <= '0';
wait for my_time/2;

if (it = Iterations) then sign := -1;
elsif (it = 0) then sign := +1;
end if;

it := it + sign*1;
end loop;
end process;

end generate SSC_GENERATE;

NO_SSC_GENERATE: if (SSC_ENABLE = FALSE) generate
-- Generate Reference Clock input (250MHz)
process begin
refclk_n_r <= '1';
wait for REFCLK_PERIOD/2;
refclk_n_r <= '0';
wait for REFCLK_PERIOD/2;
end process;
end generate;

refclk_p_r <= not refclk_n_r;

Good luck!
Cristian
 

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