Can port Maps be expressions?

[Shannon]

Does VHDL allow expressions in port maps? For example see 'cnt_en'
below:

lockout_count: ENTITY work.counter_16
PORT MAP(
clock => MClk,
cnt_en => lockout_cnt_en AND NOT lockout_eq0,
data => STD_LOGIC_VECTOR(LOCKOUT_TIME),
sload => lockout_sload,
q => lockout_cnt
);

Shannon

 

[Shannon]

No, not currently

Alan

P.S. The feature is introduced in VHDL2008 which should be standardised
by the IEEE this year.

Thank you.

 

[Andy]

The "type conversion" need not be just a type conversion. It must be a
function with exactly one argument, and the return type of the
function must be constrained.

For example, invert(lockout_time) would also work, if invert() returns
a constrained type. The data type need not actually change.

The same restriction applies to a type conversion, unless it is an
implicit conversion (e.g. from numeric_std.unsigned to SLV).

I saw a paper several years ago that used conversion functions in
configuration port maps to allow substitution of integer vs vector
based models.

Andy