Can wild letters be used in case statements?

[fl]

Hi,

I am implementing 7 lookup tables, which compose a large table. In this way, the resource used only depends on the table values. I only list one lut component: lut6 to save space below.

You can see that s_addr6(5:0) is ignored. This is a 64 to 1 saving for the table (These 64 addresses have one same lut output).

I use Modelsim 6.5 SE. The problem is that it seems that the case always select "when others " line. Even though tmp value is "000011100000001" (15 bits), it does not use o_tmp_2 output.

This case statement originates from "The designer's guide to VHDL" book.
In the example snippet on the book, it uses "case?". But Xilinx ISE does not understand "case?".



Could you help me on this problem?

Thanks,





signal tmp : unsigned(14 DOWNTO 0);
signal o_tmp0 : std_logic_vector(25 DOWNTO 0);
signal o_tmp1 : std_logic_vector(25 DOWNTO 0);
signal o_tmp2 : std_logic_vector(25 DOWNTO 0);
signal o_tmp3 : std_logic_vector(25 DOWNTO 0);
signal o_tmp4 : std_logic_vector(25 DOWNTO 0);
signal o_tmp5 : std_logic_vector(25 DOWNTO 0);
signal o_tmp6 : std_logic_vector(25 DOWNTO 0);

signal o_tmp_0 : unsigned(25 DOWNTO 0);
signal o_tmp_1 : unsigned(25 DOWNTO 0);
signal o_tmp_2 : unsigned(25 DOWNTO 0);
signal o_tmp_3 : unsigned(25 DOWNTO 0);
signal o_tmp_4 : unsigned(25 DOWNTO 0);
signal o_tmp_5 : unsigned(25 DOWNTO 0);
signal o_tmp_6 : unsigned(25 DOWNTO 0);

signal s_addr0 : unsigned(8 DOWNTO 0);
signal s_addr1 : unsigned(7 DOWNTO 0);
signal s_addr2 : unsigned(7 DOWNTO 0);
signal s_addr3 : unsigned(7 DOWNTO 0);
signal s_addr4 : unsigned(7 DOWNTO 0);
signal s_addr5 : unsigned(7 DOWNTO 0);
signal s_addr6 : unsigned(7 DOWNTO 0);
signal lut_reciprocal_internal : unsigned(25 DOWNTO 0);






lut6 : kalman_fadd_lut6 port map (
clk => clk,
reset => reset,
enb_1_1_1 => '1',
divider_u => std_logic_vector(s_addr6),
lut_reciprocal => o_tmp6);

tmp <= unsigned(divider_in(14 downto 0));
o_tmp_0 <= unsigned(o_tmp0);
o_tmp_1 <= unsigned(o_tmp1);
o_tmp_2 <= unsigned(o_tmp2);
o_tmp_3 <= unsigned(o_tmp3);
o_tmp_4 <= unsigned(o_tmp4);
o_tmp_5 <= unsigned(o_tmp5);
o_tmp_6 <= unsigned(o_tmp6);

s_addr0 <= tmp( 8 downto 0);
s_addr1 <= tmp( 8 downto 1);
s_addr2 <= tmp( 9 downto 2);
s_addr3 <= tmp(10 downto 3);
s_addr4 <= tmp(11 downto 4);
s_addr5 <= tmp(12 downto 5);
s_addr6 <= tmp(13 downto 6);



PROCESS(tmp)
BEGIN
CASE tmp IS
-- lut: 15 address bus
when "1--------------" => lut_reciprocal_internal <= o_tmp_6;
when "01-------------" => lut_reciprocal_internal <= o_tmp_5;
when "001------------" => lut_reciprocal_internal <= o_tmp_4;
when "0001-----------" => lut_reciprocal_internal <= o_tmp_3;
when "00001----------" => lut_reciprocal_internal <= o_tmp_2;
when "000001---------" => lut_reciprocal_internal <= o_tmp_1;
WHEN OTHERS => lut_reciprocal_internal <= o_tmp_0;
END CASE;
END PROCESS;

 

[Jim Lewis]

Unfortunately Xilinx has been focusing on Vivado.

VHDL-2008 is the only easy avenue to your circuit. Make sure to submit it as a bug to Xilinx. Also be sure to refer to the Mentor study which shows that 70% of FPGA RTL designers use VHDL, so how come they are lagging so far behind in implementing the VHDL-2008 standard.

 

[Jim Lewis]

Unfortunately Xilinx has been focusing on Vivado.

VHDL-2008 is the only easy avenue to your circuit. Make sure to submit it as a bug to Xilinx. Also be sure to refer to the Mentor study which shows that 70% of FPGA RTL designers use VHDL, so how come they are lagging so far behind in implementing the VHDL-2008 standard.

Altera documentation indicates that they do support the matching case statement (Case?).

 

[fl]

Unfortunately Xilinx has been focusing on Vivado.



VHDL-2008 is the only easy avenue to your circuit. Make sure to submit it as a bug to Xilinx. Also be sure to refer to the Mentor study which shows that 70% of FPGA RTL designers use VHDL, so how come they are lagging so far behind in implementing the VHDL-2008 standard.



Altera documentation indicates that they do support the matching case statement (Case?).

Thanks. The if then can get the function but with a large cascaded delay. As Xilinx does not support it, can I construct such functionality by myself?
I have no idea on how to do that now. Please shed some light on it if you know.

 

[Nicolas Matringe]

Le 20/02/2014 20:28, fl a écrit :

Hi,

I am implementing 7 lookup tables, which compose a large table. In this way, the resource used only depends on the table values. I only list one lut component: lut6 to save space below.

PROCESS(tmp)
BEGIN
CASE tmp IS
-- lut: 15 address bus
when "1--------------" => lut_reciprocal_internal <= o_tmp_6;
when "01-------------" => lut_reciprocal_internal <= o_tmp_5;
when "001------------" => lut_reciprocal_internal <= o_tmp_4;
when "0001-----------" => lut_reciprocal_internal <= o_tmp_3;
when "00001----------" => lut_reciprocal_internal <= o_tmp_2;
when "000001---------" => lut_reciprocal_internal <= o_tmp_1;
WHEN OTHERS => lut_reciprocal_internal <= o_tmp_0;
END CASE;
END PROCESS;

Hi
Seems to me you'd be better off with cascaded if...then...elsif...
statements in this particular case.

Nicolas

 

[Gabor]

Thanks. The if then can get the function but with a large cascaded delay. As Xilinx does not support it, can I construct such functionality by myself?
I have no idea on how to do that now. Please shed some light on it if you know.

Not clear what you mean by a "large cascaded delay." Any reasonable
synthesis engine will create the same logic whether you use a case
statement or the equivalent if ... elsif ... else statements.

 

[fl]

Not clear what you mean by a "large cascaded delay." Any reasonable

synthesis engine will create the same logic whether you use a case

statement or the equivalent if ... elsif ... else statements.

Excuse me, I am new to VHDL yet. On some VHDL books, it shows me that "if then else" structure will generate cascaded muxes (i.e. there is priorities in "if...then...else" structures. Because of the cascaded muxes, the delay will be larger), while "when... case..." generates no priority structures (All cases are exclusive with each other and combined to the whole set. Thisstructure uses more resources but less delay). I will check the book and check the implementation results later. Thanks for your comments.

 

[Tobias Baumann]

Am 25.02.2014 01:32, schrieb fl:

Excuse me, I am new to VHDL yet. On some VHDL books, it shows me that "if then else" structure will generate cascaded muxes (i.e. there is priorities in "if...then...else" structures. Because of the cascaded muxes, the delay will be larger), while "when... case..." generates no priority structures (All cases are exclusive with each other and combined to the whole set. This structure uses more resources but less delay). I will check the book and check the implementation results later. Thanks for your comments.

Generally that's right. But if you use in every if statement the same
signal/variable, then the if ... elsif ... else is equivalent to a case
structure.

For example:

if (tmp = "0001") then
...
elsif (tmp = "0010") then
...
else
...
end if;

should produce the same synthesis output then

case tmp is
when "0001" => ...
when "0010" => ...
when others => ...
end case;

You can produce a small example project and implement both structures.
My synthesis tool (Xilinx XST Version 14.x) works like expected.

I use this approach really often to avoid "locally static" warnings in
case statements.

Tobias

 

[HT-Lab]

Thanks. The if then can get the function but with a large cascaded delay. As Xilinx does not support it, can I construct such functionality by myself?
I have no idea on how to do that now. Please shed some light on it if you know.

If I understand this Xilinx answer record correctly, VHDL2008 synthesis
will not be supported until 2014.3 which probably means end of this year.

http://www.xilinx.com/support/answers/51502.html

If you have some budget I would suggest you have a word with
Mentor/Synplify to get hold of a proper synthesis tool.

Good luck,
Hans
www.ht-lab.com