Can you implement a pull-up resistor in VHDL?

Discussion in 'VHDL' started by jidan1@hotmail.com, Dec 4, 2007.

  1. Guest

    Hello,

    I am using Spartan-3 XC31000. You can enable on/off pull-up/pull-down
    resistors with ISE; however, i would like to do this in VHDL so that i
    can enable them during runtime. At first I thought these lines would
    synthese, but I was wrong.


    entity pullup is
    port (inp_i :in std_logic;
    outp_o : out std_logic);
    end pullup;

    architecture rtl of pullup is
    signal s_inp_i : std_logic;
    begin
    s_inp_i <= 'H';
    s_inp_i <= inp_i;
    outp_o <= inp_i;
    end rtl;

    Any Idea how to do this?

    Thanks;
    JJ
     
    , Dec 4, 2007
    #1
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  2. Peter Guest

    >
    > Any Idea how to do this?
    >

    Hi,

    I am not familiar with Xilinx software, but when designing with e.g.
    Actel you instantiate a certain I/O-pad in your vhdl code.

    /Peter
     
    Peter, Dec 4, 2007
    #2
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  3. Jan Guest

    Jan, Dec 4, 2007
    #3
  4. Dave Pollum Guest

    On Dec 4, 8:48 am, wrote:
    > Hello,
    >
    > I am using Spartan-3 XC31000. You can enable on/off pull-up/pull-down
    > resistors with ISE; however, i would like to do this in VHDL so that i
    > can enable them during runtime. At first I thought these lines would
    > synthese, but I was wrong.
    >
    > entity pullup is
    > port (inp_i :in std_logic;
    > outp_o : out std_logic);
    > end pullup;
    >
    > architecture rtl of pullup is
    > signal s_inp_i : std_logic;
    > begin
    > s_inp_i <= 'H';
    > s_inp_i <= inp_i;
    > outp_o <= inp_i;
    > end rtl;
    >
    > Any Idea how to do this?
    >
    > Thanks;
    > JJ


    I don't know how to implement pull-up/pull-down, but you can't assign
    values to input port "inp_i".
    -Dave Pollum
     
    Dave Pollum, Dec 4, 2007
    #4
  5. Dave Pollum wrote:

    > but you can't assign
    > values to input port "inp_i".


    And he hasn't... ?!?

    Regards,

    --
    Mark McDougall, Engineer
    Virtual Logic Pty Ltd, <http://www.vl.com.au>
    21-25 King St, Rockdale, 2216
    Ph: +612-9599-3255 Fax: +612-9599-3266
     
    Mark McDougall, Dec 5, 2007
    #5
  6. wrote:

    > I am using Spartan-3 XC31000. You can enable on/off pull-up/pull-down
    > resistors with ISE; however, i would like to do this in VHDL so that i
    > can enable them during runtime.


    Are you talking about having "pull-ups" _inside_ the FPGA, which can be
    turned on/off whilst the image is running?

    I've done a few designs with an "open-collector" bus connecting several
    internal modules, plus an external IO... each internal module uses the
    "resolved" bus signal as input, and drives "oe" as an output. The
    top-level "resolved" signal is computed combinatorially from the external
    input plus the internal oe signals... and of course the oe's combine to
    drive the I/O pin direction as well.

    Regards,

    --
    Mark McDougall, Engineer
    Virtual Logic Pty Ltd, <http://www.vl.com.au>
    21-25 King St, Rockdale, 2216
    Ph: +612-9599-3255 Fax: +612-9599-3266
     
    Mark McDougall, Dec 5, 2007
    #6
  7. Guest


    > Are you talking about having "pull-ups" _inside_ the FPGA, which can be
    > turned on/off whilst the image is running?


    Exactly. But it seems that it's unfortunatly not possible while the
    FPGA is running; it has to be done during configuration ;(

    JJ
     
    , Dec 5, 2007
    #7
  8. Jan wrote:
    > You cannot dynamically enable/disable pullups in xilinx devices.
    > You can instantiate a PULLUP/PULLDOWN primitive, but it cannot change
    > after configuration..
    > see http://toolbox.xilinx.com/docsan/xilinx9/books/docs/s3edl/s3edl.pdf


    For Virtex series it might be possible to do this with dynamic
    reconfiguration. But for Spartan the pullup/down is not
    dynamic setting.

    --Kim
     
    Kim Enkovaara, Dec 5, 2007
    #8
  9. Dave Pollum Guest

    On Dec 4, 10:25 pm, Mark McDougall <> wrote:
    > Dave Pollum wrote:
    > > but you can't assign
    > > values to input port "inp_i".

    >
    > And he hasn't... ?!?
    >
    > Regards,
    >
    > --
    > Mark McDougall, Engineer
    > Virtual Logic Pty Ltd, <http://www.vl.com.au>
    > 21-25 King St, Rockdale, 2216
    > Ph: +612-9599-3255 Fax: +612-9599-3266


    DOH! I missed "s_inp_i". Next time I'll be sure to wear my glasses!
    -Dave Pollum
     
    Dave Pollum, Dec 5, 2007
    #9
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