Can you implement a pull-up resistor in VHDL?

[jidan1]

Hello,

I am using Spartan-3 XC31000. You can enable on/off pull-up/pull-down
resistors with ISE; however, i would like to do this in VHDL so that i
can enable them during runtime. At first I thought these lines would
synthese, but I was wrong.


entity pullup is
port (inp_i :in std_logic;
outp_o : out std_logic);
end pullup;

architecture rtl of pullup is
signal s_inp_i : std_logic;
begin
s_inp_i <= 'H';
s_inp_i <= inp_i;
outp_o <= inp_i;
end rtl;

Any Idea how to do this?

Thanks;
JJ

 

[Peter]

Any Idea how to do this?

Hi,

I am not familiar with Xilinx software, but when designing with e.g.
Actel you instantiate a certain I/O-pad in your vhdl code.

/Peter

 

[Jan]

You cannot dynamically enable/disable pullups in xilinx devices.
You can instantiate a PULLUP/PULLDOWN primitive, but it cannot change
after configuration..
see http://toolbox.xilinx.com/docsan/xilinx9/books/docs/s3edl/s3edl.pdf

 

[Dave Pollum]

Hello,

I am using Spartan-3 XC31000. You can enable on/off pull-up/pull-down
resistors with ISE; however, i would like to do this in VHDL so that i
can enable them during runtime. At first I thought these lines would
synthese, but I was wrong.

entity pullup is
port (inp_i :in std_logic;
outp_o : out std_logic);
end pullup;

architecture rtl of pullup is
signal s_inp_i : std_logic;
begin
s_inp_i <= 'H';
s_inp_i <= inp_i;
outp_o <= inp_i;
end rtl;

Any Idea how to do this?

Thanks;
JJ

I don't know how to implement pull-up/pull-down, but you can't assign
values to input port "inp_i".
-Dave Pollum

 

[Mark McDougall]

but you can't assign
values to input port "inp_i".

And he hasn't... ?!?

Regards,

 

[Mark McDougall]

I am using Spartan-3 XC31000. You can enable on/off pull-up/pull-down
resistors with ISE; however, i would like to do this in VHDL so that i
can enable them during runtime.

Are you talking about having "pull-ups" _inside_ the FPGA, which can be
turned on/off whilst the image is running?

I've done a few designs with an "open-collector" bus connecting several
internal modules, plus an external IO... each internal module uses the
"resolved" bus signal as input, and drives "oe" as an output. The
top-level "resolved" signal is computed combinatorially from the external
input plus the internal oe signals... and of course the oe's combine to
drive the I/O pin direction as well.

Regards,

 

[jidan1]

Are you talking about having "pull-ups" _inside_ the FPGA, which can be
turned on/off whilst the image is running?

Exactly. But it seems that it's unfortunatly not possible while the
FPGA is running; it has to be done during configuration ;(

JJ

 

[Kim Enkovaara]

You cannot dynamically enable/disable pullups in xilinx devices.
You can instantiate a PULLUP/PULLDOWN primitive, but it cannot change
after configuration..
see http://toolbox.xilinx.com/docsan/xilinx9/books/docs/s3edl/s3edl.pdf

For Virtex series it might be possible to do this with dynamic
reconfiguration. But for Spartan the pullup/down is not
dynamic setting.

--Kim

 

[Dave Pollum]

And he hasn't... ?!?

Regards,

--
Mark McDougall, Engineer
Virtual Logic Pty Ltd, <http://www.vl.com.au>
21-25 King St, Rockdale, 2216
Ph: +612-9599-3255 Fax: +612-9599-3266

DOH! I missed "s_inp_i". Next time I'll be sure to wear my glasses!
-Dave Pollum