Cannot find function "TO_INTEGER" for these actuals

Discussion in 'VHDL' started by Travis, Jun 15, 2013.

  1. Travis

    Travis Guest

    Hi all, I'm compiling the following VHDL to make a simple ROM, and I'm getting these errors:
    # Error: COMP96_0305: SUBONE_MODULE_VHDL.vhd : (93, 23): Cannot find function "TO_INTEGER" for these actuals.
    # Error: COMP96_0138: SUBONE_MODULE_VHDL.vhd : (93, 23): The index types in the reference to the array object are incompatible with its range type.

    I'm using Active-HDL 9.2. This was based off an example I got online, but I had to switch to the NUMERIC_STD IEEE library because I want to synthesize this.

    Thanks!

    library IEEE;
    use IEEE.STD_LOGIC_1164.all;
    use IEEE.NUMERIC_STD.all;


    entity SUBONE_MODULE_VHDL is
    port(
    addr : in STD_LOGIC_VECTOR(4 downto 0);
    clk : in STD_LOGIC;
    dout : out STD_LOGIC_VECTOR(4 downto 0)
    );
    end SUBONE_MODULE_VHDL;

    --}} End of automatically maintained section

    architecture SUBONE_MODULE_VHDL of SUBONE_MODULE_VHDL is

    -- enter your statements here --

    type ROM_Array is array (0 to 31)
    of std_logic_vector(4 downto 0);


    constant Content: ROM_Array := (
    0 => "10011", -- Suppose ROM has
    1 => "00000", -- prestored value
    2 => "00001", -- like this table
    3 => "00010", --
    4 => "00011", --
    5 => "00100", --
    6 => "00101", --
    7 => "00110", --
    8 => "00111", --
    9 => "01000", --
    10 => "01001", --
    11 => "01010", --
    12 => "01011", --
    13 => "01100", --
    14 => "01101", --
    15 => "01110", --
    16 => "01111", --
    17 => "01110", --
    18 => "01110", --
    19 => "01110", --
    20 => "01110", --
    21 => "00000", --
    22 => "00001", --
    23 => "00010", --
    24 => "00011", --
    25 => "00100", --
    26 => "00101", --
    27 => "00110", --
    28 => "00111", --
    29 => "01000", --
    30 => "01001", --
    31 => "01010", --
    OTHERS => "00000"
    );

    begin
    process(clk, addr)
    variable addr : integer := 0;
    begin
    if( clk'event and clk = '1' ) then
    dout <= Content(TO_INTEGER(addr));
    end if;
    end process;


    end SUBONE_MODULE_VHDL;
     
    Travis, Jun 15, 2013
    #1
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  2. Travis

    KJ Guest

    You have...

    dout <= Content(TO_INTEGER(addr));

    should be...

    dout <= Content(TO_INTEGER(unsigned(addr)));

    The reason is that addr is defined to be a std_logic_vector. Std_logic_vector has no numeric interpretation it is just an arbitrary collection of bits. By casting it as 'unsigned' you are saying to interpret it as an unsigned numeric quantity which can then be converted to an integer value.

    Kevin Jennings
     
    KJ, Jun 15, 2013
    #2
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  3. Travis

    Travis Guest

    Thank you so much! I'll try it ASAP and report back!

    On Friday, June 14, 2013 7:47:28 PM UTC-7, KJ wrote:
    > You have...
    >
    >
    >
    > dout <= Content(TO_INTEGER(addr));
    >
    >
    >
    > should be...
    >
    >
    >
    > dout <= Content(TO_INTEGER(unsigned(addr)));
    >
    >
    >
    > The reason is that addr is defined to be a std_logic_vector. Std_logic_vector has no numeric interpretation it is just an arbitrary collection of bits. By casting it as 'unsigned' you are saying to interpret it as an unsigned numeric quantity which can then be converted to an integer value.
    >
    >
    >
    > Kevin Jennings
     
    Travis, Jun 15, 2013
    #3
  4. Travis

    Andy Guest

    Travis,

    You also need to remove the unused variable declaration for addr in the process. It is hiding the addr port.

    Andy
     
    Andy, Jun 17, 2013
    #4
  5. Travis

    Travis Guest

    Hi Andy,

    I just tried Kevin's solution, noticed the error, got bummed, noticed your solution, and now all is fixed. Thank you both!

    Andy & Kevin, if I could ask, it appears I was interpreting what "variable addr : integer;" was doing. I thought it was providing context for use of "addr" within the process block, but this is apparently incorrect. Do you have a good reference or pointer for these types of things?

    Thanks again!

    On Monday, June 17, 2013 5:57:45 AM UTC-7, Andy wrote:
    > Travis,
    >
    >
    >
    > You also need to remove the unused variable declaration for addr in the process. It is hiding the addr port.
    >
    >
    >
    > Andy
     
    Travis, Jun 17, 2013
    #5
  6. Travis

    Guest

    Another option is to make the input 'unsigned', which is a better type in this context.
     
    , Jun 17, 2013
    #6
  7. Travis

    Andy Guest

    Variables are storage objects that are usually local to processes or subprograms where they are declared. They are assigned using ":=" instead of "<=". Their value updates immediately upon execution of the assignment statement, instead of waiting until the process suspends, like signal values do.

    Most VHDL texts cover variables, but most will tell you not to use them forRTL (or at least not for registers in RTL), which is unfortunate, since variables are quite powerful for both combinatorial and register logic, once you know how to use them.

    Andy
     
    Andy, Jun 17, 2013
    #7
  8. Travis

    Andy Guest

    What Kevin said (make addr unsigned).

    Or, if your tools support vhdl-2008, you can use the new package ieee.numeric_std_unsigned.all, and use to_integer(addr) without converting (or changing) addr to unsigned.

    Andy
     
    Andy, Jun 17, 2013
    #8
  9. Travis

    Travis Guest

    Xilinx ISE won't be supporting VHDL 2008 at all, apparently they're reserving that for the Vivado tools, which is truly sad because it looks like VHDL2008 is a meaningful update.

    On Monday, June 17, 2013 10:28:03 AM UTC-7, Andy wrote:
    > What Kevin said (make addr unsigned).
    >
    >
    >
    > Or, if your tools support vhdl-2008, you can use the new package ieee.numeric_std_unsigned.all, and use to_integer(addr) without converting (or changing) addr to unsigned.
    >
    >
    >
    > Andy
     
    Travis, Jun 18, 2013
    #9
  10. Travis

    Guest

    And who knows how much 2008 Vivado really supports. Probably not much. Use Synplify, if possible. The VHDL 2008 additions are indispensable. One thing I could not do without is the fixed-point package.
     
    , Jun 18, 2013
    #10
  11. Travis

    Travis Guest

    I will examine the Synopsys tools; I'm converting a design that is largely schematic based in Active-HDL (that has components that date back to Active-CAD) to VHDL, and there are numerous headaches.

    On Tuesday, June 18, 2013 9:59:08 AM UTC-7, wrote:
    > And who knows how much 2008 Vivado really supports. Probably not much. Use Synplify, if possible. The VHDL 2008 additions are indispensable. One thing I could not do without is the fixed-point package.
     
    Travis, Jun 18, 2013
    #11
  12. Travis

    Guest

    I've had to do the same thing, but years ago. I assumed nobody was using schematics anymore. I do see a lot of HDL that looks like schematic netlists.
     
    , Jun 18, 2013
    #12
  13. Travis

    Travis Guest

    Schematics are great from a top down perspective, "The block does this", etc, but the design I'm converting has AND, OR, inverters, Virtex specific buffers, etc sprinkled throughout it.

    We're using Active-HDL, and we have uncovered SO many problems with the tool it is ridiculous. Apparently so few people do it this way they're dropping support for updated Xilinx schematic input in Active-HDL 9.3.


    On Tuesday, June 18, 2013 12:04:40 PM UTC-7, wrote:
    > I've had to do the same thing, but years ago. I assumed nobody was using schematics anymore. I do see a lot of HDL that looks like schematic netlists.
     
    Travis, Jun 18, 2013
    #13
  14. Travis

    rickman Guest

    On 6/18/2013 12:45 PM, Travis wrote:
    > Xilinx ISE won't be supporting VHDL 2008 at all, apparently they're reserving that for the Vivado tools, which is truly sad because it looks like VHDL2008 is a meaningful update.


    That is pretty amazing! I can't believe Xilinx is ignoring VHDL 2008.
    I am coding in VHDL 2008 and expect my tools to support that.

    I don't have any trouble with the Lattice tools including the Active-HDL
    simulator. I was working with the iceCube tool for the iCE40 parts, but
    haven't done anything with VHDL 2008 in the main line devices. I may
    try it with the current design I'm working on. I need to get a new
    laptop and will install the newer tools on it and give VHDL 2008 a run
    under Diamond.

    --

    Rick
     
    rickman, Jun 20, 2013
    #14
  15. Travis

    Anssi Saari Guest

    rickman <> writes:

    > On 6/18/2013 12:45 PM, Travis wrote:
    >> Xilinx ISE won't be supporting VHDL 2008 at all, apparently they're reserving that for the Vivado tools, which is truly sad because it looks like VHDL2008 is a meaningful update.

    >
    > That is pretty amazing! I can't believe Xilinx is ignoring VHDL
    > 2008. I am coding in VHDL 2008 and expect my tools to support that.


    I'd also expect Xilinx to support at least the fixed point stuff in ISE.
    Didn't everyone add that almost overnight?
     
    Anssi Saari, Jun 24, 2013
    #15
  16. Travis

    Guest

    Theoretically, the fixed point library shouldn't require any special synthesizer support but I wouldn't be surprised if ISE didn't like it for some reason. I definitely wouldn't try it with unconstrained i/o. And, as with integer math functions, I wouldn't expect it to map to DSP48s very well.
     
    , Jun 24, 2013
    #16
  17. Travis

    Andy Guest

    Unconstrained IO fixed point should work fine, since the bound object is static and therefore it's index range is static too. Just be real careful with bit string literals! (e.g. don't use bit string literals for fixed/floating point).

    Fixed point arithmetic is implemented using numeric_std operators, so it should do fine for anything

    IIRC, some synthesis tools had problems with fixed point because they did not support negative indices on arrays (slv/signed/unsigned have natural index ranges). There are '93 compatible versions of the fixed point package available, they just don't support package generics for saturate/rollover or round/truncate and number of guard bits for division. You have to change the constants in the '93 package.

    Andy
     
    Andy, Jun 25, 2013
    #17
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