Case choice must be a locally static expression

Discussion in 'VHDL' started by Peter, Feb 17, 2011.

  1. Peter

    Peter Guest

    Hi,

    I have searched the net for the above mentioned warning from Modelsim,
    but I cant really understand whats the problem.

    I have declared some constants in a package:

    Constant MASKREG : unsigned(5 downto 0):= To_unsigned(0,6);
    Constant CONTREG : unsigned(5 downto 0):= To_unsigned(1,6);
    ......

    They are used in a procedure in another entity:

    Procedure write_register is
    Begin
    case adr is
    when MASKREG => mask := shreg(mask'range);
    when CONTREG => cont := shreg(cont'range);
    when DEADTIMEREG => deadtime := shreg(deadtime'range);
    when FILTLOREG => filtlo := shreg(filtlo'range);
    when FILTHIREG => filthi := shreg(filthi'range);
    when MISCREG => misc := shreg(misc'range);
    when others => null;
    end case;
    End procedure write_register;

    Why is the case choice not considered locally static by Modelsim?

    Thanks in advance.

    /Peter
     
    Peter, Feb 17, 2011
    #1
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  2. Peter

    Peter Guest

    However, replacing then constant declaration with the code below,
    makes the warning disappear:

    Constant MASKREG : unsigned(5 downto 0):= "000000";
    Constant CONTREG : unsigned(5 downto 0):= "000001";

    So the problem seems to be the To_unsigned function?

    /Peter
     
    Peter, Feb 17, 2011
    #2
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  3. Peter

    Tricky Guest

    On Feb 17, 8:39 am, Peter <> wrote:
    > Hi,
    >
    > I have searched the net for the above mentioned warning from Modelsim,
    > but I cant really understand whats the problem.
    >
    > I have declared some constants in a package:
    >
    > Constant MASKREG        : unsigned(5 downto 0):= To_unsigned(0,6);
    > Constant CONTREG        : unsigned(5 downto 0):= To_unsigned(1,6);
    > .....
    >
    > They are used in a procedure in another entity:
    >
    > Procedure write_register is
    > Begin
    >    case adr is
    >      when MASKREG        =>  mask      := shreg(mask'range);
    >      when CONTREG         =>  cont        := shreg(cont'range);
    >      when DEADTIMEREG =>  deadtime := shreg(deadtime'range);
    >      when FILTLOREG       =>  filtlo         := shreg(filtlo'range);
    >      when FILTHIREG        =>  filthi         := shreg(filthi'range);
    >      when MISCREG         =>  misc        := shreg(misc'range);
    >      when others               =>  null;
    >    end case;
    > End procedure write_register;
    >
    > Why is the case choice not considered locally static by Modelsim?
    >
    > Thanks in advance.
    >
    > /Peter


    Ive seen exactly the same warning with std_logic_vector constants
    declared in a package (and declared explicitly without a conversion
    function). I can only guess that its scared you could go and change
    the constant. But I dont get it.
     
    Tricky, Feb 17, 2011
    #3
  4. Peter

    HT-Lab Guest


    >"Peter" wrote in message
    >news:...
    >
    >Hi,
    >
    >I have searched the net for the above mentioned warning from Modelsim,
    >but I cant really understand whats the problem.
    >
    >I have declared some constants in a package:
    >
    >Constant MASKREG : unsigned(5 downto 0):= To_unsigned(0,6);
    >Constant CONTREG : unsigned(5 downto 0):= To_unsigned(1,6);
    >.....
    >
    >They are used in a procedure in another entity:
    >
    >Procedure write_register is
    >Begin
    > case adr is
    > when MASKREG => mask := shreg(mask'range);
    > when CONTREG => cont := shreg(cont'range);
    > when DEADTIMEREG => deadtime := shreg(deadtime'range);
    > when FILTLOREG => filtlo := shreg(filtlo'range);
    > when FILTHIREG => filthi := shreg(filthi'range);
    > when MISCREG => misc := shreg(misc'range);
    > when others => null;
    > end case;
    >End procedure write_register;
    >
    >Why is the case choice not considered locally static by Modelsim?
    >
    >Thanks in advance.


    What happens if you compile under VHDL2008? (you need Modelsim 10.0)

    Hans
    www.ht-lab.com

    /Peter
     
    HT-Lab, Feb 17, 2011
    #4
  5. On 17 Feb., 15:13, Tricky <> wrote:
    > Ive seen exactly the same warning with std_logic_vector constants
    > declared in a package (and declared explicitly without a conversion
    > function). I can only guess that its scared you could go and change
    > the constant. But I dont get it.


    You actually could change the constant. It is possible to change
    package body.
    The same constants declared in the architecture which contains the
    case will avoid this error message.

    Before vhdl2008 this is one of the most crucial limitations for
    readablity in my opinion, that you are not allowed to use constants
    from packages as case-choice. Luckyly Modelsim does just warn, but
    uses the Constant.

    bye Thomas
     
    Thomas Stanka, Feb 17, 2011
    #5
  6. Peter

    HT-Lab Guest

    >"Thomas Stanka" wrote in message
    >news:...
    >
    >On 17 Feb., 15:13, Tricky <> wrote:

    ...>
    >You actually could change the constant. It is possible to change
    >package body.
    >The same constants declared in the architecture which contains the
    >case will avoid this error message.
    >
    >Before vhdl2008 this is one of the most crucial limitations for
    >readablity in my opinion, that you are not allowed to use constants
    >from packages as case-choice. Luckyly Modelsim does just warn, but
    >uses the Constant.


    With VHDL2008 you also no longer get the warning, I just created a quick
    test case based on Peter's code and with Modelsim I get:

    D:\Modelsim>vcom -2002 locally_static.vhd
    Model Technology ModelSim DE vcom 10.0 Compiler 2010.12 Dec 4 2010
    -- Compiling entity x
    -- Compiling architecture rtl of x
    ** Warning: locally_static.vhd(18): Choice in CASE statement alternative
    must be locally static.

    D:\Modelsim>vcom -2008 locally_static.vhd
    Model Technology ModelSim DE vcom 10.0 Compiler 2010.12 Dec 4 2010
    -- Compiling entity x
    -- Compiling architecture rtl of x

    Simple testcase shown below,

    Hans
    www.ht-lab.com


    library ieee;
    use ieee.std_logic_1164.all;
    use ieee.numeric_std.all;

    entity x is
    end x;

    architecture rtl of x is

    constant maskreg : unsigned(5 downto 0):= to_unsigned(0,6);
    signal shreg : unsigned(5 downto 0);

    procedure write_register(adr:in unsigned(5 downto 0)) is
    variable mask:unsigned(5 downto 0);
    begin
    case adr is
    when maskreg => mask := shreg(mask'range); -- Line18
    when others => null;
    end case;
    end procedure write_register;

    begin
    end rtl;

    >bye Thomas
     
    HT-Lab, Feb 17, 2011
    #6
  7. Peter

    Peter Guest

    >
    > Before vhdl2008 this is one of the most crucial limitations for
    > readablity in my opinion, that you are not allowed to use constants
    > from packages as case-choice. Luckyly Modelsim does just warn, but
    > uses the Constant.
    >
    > bye Thomas


    But it seems as constants in a package are allowed in a case-choice,
    as long as I dont use the "to_unsigned" function?

    Constant MASKREG : unsigned(5 downto 0):= "000000"; --
    Gives no warning
    Constant MASKREG : unsigned(5 downto 0):= To_unsigned(0,6); --
    Does

    The package is compiled first. Why is the compiler unable to know the
    value of the constant just because it was set by a function?

    And I tried to move the declaration into the architecture where it is
    used. It gives the same warning.

    Thanks gentlemen for Your interest,

    Peter
     
    Peter, Feb 18, 2011
    #7
  8. Peter

    Thomas Rouam Guest

    On Feb 18, 7:33 am, Peter <> wrote:
    > > Before vhdl2008 this is one of the most crucial limitations for
    > > readablity in my opinion, that you are not allowed to use constants
    > > from packages as case-choice. Luckyly Modelsim does just warn, but
    > > uses the Constant.

    >
    > > bye Thomas

    >
    > But it seems as constants in a package are allowed in a case-choice,
    > as long as I dont use the "to_unsigned" function?
    >
    > Constant MASKREG        : unsigned(5 downto 0):= "000000";         --
    > Gives no warning
    > Constant MASKREG        : unsigned(5 downto 0):= To_unsigned(0,6); --
    > Does
    >
    > The package is compiled first. Why is the compiler unable to know the
    > value of the constant just because it was set by a function?
    >
    > And I tried to move the declaration into the architecture where it is
    > used. It gives the same warning.
    >
    > Thanks gentlemen for Your interest,
    >
    > Peter


    Hi Peter,

    The simple use of a function defined in a package makes your constant
    non locally static. On the other hand, it is globally static because
    it can resolve the constant value without having to "run" the design.
    Unfortunately for you, the case wants to be able to know the value
    within the entity it is used which is not the case.

    Regards,

    Thomas
     
    Thomas Rouam, Feb 18, 2011
    #8
  9. Peter

    JimLewis Guest

    Hi Peter,
    This was addressed in the VHDL-2008 revision. There were a
    couple of changes to the language that now allow this to be
    locally static.

    Turn on the 2008 switch in modelsim. Double check that it works
    in your synthesis tool (or tools if you are making an FPGA then
    an ASIC) and you should be ok.

    Best,
    Jim
     
    JimLewis, Feb 18, 2011
    #9
  10. Peter

    Peter Guest

    On 19 Feb, 00:22, JimLewis <> wrote:
    > Hi Peter,
    > This was addressed in the VHDL-2008 revision.  There were a
    > couple of changes to the language that now allow this to be
    > locally static.
    >
    > Turn on the 2008 switch in modelsim.  Double check that it works
    > in your synthesis tool (or tools if you are making an FPGA then
    > an ASIC) and you should be ok.
    >
    > Best,
    > Jim



    Thanks!

    Regards,

    Peter
     
    Peter, Feb 21, 2011
    #10
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