# Case of comparator "="

Discussion in 'VHDL' started by matchstick86, Jan 7, 2010.

1. ### matchstick86

Joined:
Oct 2, 2009
Messages:
19
0
Code (Text):

if a > b then
bitout <= '1';
elsif a < b then
bitout <= '0';
else
-- disregard bitout
end if;

I have a few sets of values for comparison. Because the likelihood of a pair of values being equal is there, I want to discard this result and move onto the next.

So for example, i have t(7 downto 0), and I compare t(0) with t(1), t(2) with t(3), and so forth till t(6) with t(7). This theoretically should give me a maximum of 4 bits. This process is continuous, so there will be a constant flow of 4 bits. Maybe stored as data(3 downto 0) in a register?

Now, the problem is, because there is a chance that I will get an "=" case, I would like to disregard that bit. Say, the last bit is discarded such that we have data(2 downto 0) since data(3) is buh-bye. But this data will be incomplete and will create latch (I'm actually making stuff up here. Correct me if I'm wrong).

So perhaps any guru out there would like to enlighten this lost soul? Danke schoen!

matchstick86, Jan 7, 2010

2. ### joris

Joined:
Jan 29, 2009
Messages:
152
0
I'm not exactly a guru, but yes, if you fail to set bitout to any value in a clocked process, it'll generate a latch (or a flipflop) for it.

You're describing three cases: less | greater | equal
you'll need two bits to encode these; which encoding you prefer for this depends on how you look at it; For example:

"equal bit, greater bit": (what you have, adding an equal indicator)
less: 00
greater: 01
equal: 10

"greater bit, less bit"
less: 01
greater: 10
equal: 00

Or, you can consider whether you can have two cases, like:
greater | less-or-equal
less | equal-or-greater

joris, Jan 7, 2010