Case range with bitstream: VHDL

Discussion in 'VHDL' started by lightofspace, Oct 31, 2006.

  1. lightofspace

    lightofspace

    Joined:
    Oct 19, 2006
    Messages:
    8
    Hi there!!
    I am stuck in a problem of CASE range, I have the following code:
    ----------------------------------------------------------------------------
    input_data: IN std_logic_vector (7 downto 0);
    output: OUT std_logic_vector (3 downto 0);
    .
    .
    .
    .
    case input_data is
    when "00000001" => output <= "0010";
    when "10000000" to "11111111" => output <= "1000";
    when others => output <= "1111";
    end case;
    ----------------------------------------------------------------------------
    I want to make case range facility to work with binary also, how can I do this?
    thanks in advance,
    ahmad
     
    lightofspace, Oct 31, 2006
    #1
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