Case Statement difficult

Discussion in 'VHDL' started by DPettit, Oct 22, 2006.

  1. DPettit

    DPettit

    Joined:
    Oct 22, 2006
    Messages:
    1
    I am writing a program for a 4bit ALU and I am trying to get the add with carry porition right. The specific case looks like

    when "0001" => output <= ('0' & ALUin_a) + ( '0' & ALUin_b ) + cin;
    ALU_out <= output((width-1) downto 0);
    set <= output(width); reset <= not(output(width));

    The problem is that I have coded a set reset latch to retain the cout bit and use the value of it in the cin. The latch is done in a seperate process as such:

    Latch : process (set, reset)
    begin
    if (set = '1' and reset = '0') then
    Cout <= '1'; cin <= '1';
    elsif (set = '0' and reset = '1') then
    Cout <= '0'; cin <= '0';
    end if;
    end process Latch;

    The case statement seems to be executing the 3 statements concurrently and that is making the Cin what ever is the carry for the current add operation not the previous. How can I change this so the cin that is being used is from the previous add? Any help is appreciated :)
    DPettit, Oct 22, 2006
    #1
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