case statement

Discussion in 'VHDL' started by kapil_kaushik, Jun 18, 2004.

  1. can we use a case statement inside another case or if statement???
     
    kapil_kaushik, Jun 18, 2004
    #1
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  2. Officially yes (ieee 1076 Annexe A, sequential_statement, if_statement,
    case_statement_alternative, sequence_of_statement, and 1076.6),

    But now your code can become a little bit confusing if you have too lot
    of imbrication.

    Do you have a problem with them ?

    Rgrds,
    JaI

    kapil_kaushik wrote:

    >can we use a case statement inside another case or if statement???
    >
    >
    >
    >
     
    Just an Illusion, Jun 18, 2004
    #2
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  3. kapil_kaushik

    JJ Guest

    you can nest sequential statements. If your code is for rtl it can create
    sh*tloads of logic so do this sparingly.



    "kapil_kaushik" <> wrote in message
    news:...
    > can we use a case statement inside another case or if statement???
    >
    >
     
    JJ, Jun 19, 2004
    #3
  4. kapil_kaushik

    DrB Guest

    I would opine that it is the natural way to code state machines and
    suchlike:
    - outer case to lay out the current states, as choices
    - inner case (within the choices) to select the next state / outputs
    - obviously within a process, clocked and gated by an appropriate clock and
    (optional) clock enable

    If the definition of next state / output is best expressed by (further)
    nested case statements then do so. Equally, if prioritised choices are
    appropriate use if constructs. Computers are good at reducing human
    readable logic to concise boolean equations - as long as the logic is
    synchronous.

    Additionally, if the outputs are registered the use of variables for
    NextState enables the output logic to use them as inputs, simplifying the
    logic which expresses NextOutput. Using a cascade of case statements;
    firstly to define NextState, secondly to define NextOutput.

    The only serious constraints on complexity are:
    - what your simulator and synthesiser will stand
    -- Model Sim, Leonardo and Synplicity will accomodate the foregoing, others
    tools may stall
    - what your FPGA / CPLD will accomodate
    -- which reduces to a speed / size trade, do you want it in Tc or in three
    gates

    HtH

    DrB

    "kapil_kaushik" <> wrote in message
    news:...
    > can we use a case statement inside another case or if statement???
    >
    >
     
    DrB, Jun 19, 2004
    #4
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