The presence of "if reset" could imply that this is a clocked process,
not combinatorial. We can't tell because the "always" statement is not
included, and we cannot tell if the block is also sensitive to posedge
clock.
Andy- Hide quoted text -
- Show quoted text -
I have 2 case statement in 1 always loop in my verilog file. I am not
sure how this should be implemented in VHDL. I am aware of the syntax.
From design point of view I am not sure if I should be putting them in
2 seperate process statements.
Verilog =>
always @ posedge clk
c1 : case(cmd) is
when a => bunch of statements
when b => bunch of statements
when c => bunch of statements
when d => bunch of statements
default => bunch of statements
end case c1
c2 : case(cmd) is
when a => bunch of statements
when b => bunch of statements
when c => bunch of statements
when d => bunch of statements
default => bunch of statements
end case c2
end
My question is
1) Is the VHDL equivalent of the above, 2 case statements in one
process or 2 different processes with 1 case each? The problem with 2
processes I am facing is access of varaibles.
2) The above is similar to an FSM. One case statement is executing the
present command, while the other is completing the last command. Any
idea on how this should be converted to VHDL?