case when <subtype> =>

M

MikeWhy

I know there are better ways to structure a FSM, but is there a more
succinct way to write the following? For a discrete enumerated type and some
subtypes of its range, I want to write the short version, as for reds_t,
which is not legal VHDL, rather than the wordier but valid blues_t case.

case fsm_state is
...
when reds_t => -- illegal, but seems unambiguous enough
case reds_t'(fsm_state) is
when brown =>
fsm_state <= some_state;

when red =>
when orange =>
fsm_state <= some_state;

end case;
when blues_t'low to blues_t'high => -- wordy, but works
case blues_fsm in
...
end case;
when invalid =>
...
end;


given these declarations:

type state_t is (
black, brown, red, orange,
yellow, green, blue, violet,
gray, white, invalid
);
subtype reds_t is state_t range brown to orange;
subtype blues_t is state_t range green to violet;

signal fsm_state, some_state : state_t;
signal blues_fsm : blues_t;


======
 
G

goouse99

Am Freitag, 27. April 2012 06:11:25 UTC+2 schrieb MikeWhy:
I know there are better ways to structure a FSM, but is there a more
succinct way to write the following? For a discrete enumerated type and some
subtypes of its range, I want to write the short version, as for reds_t,
which is not legal VHDL, rather than the wordier but valid blues_t case.

case fsm_state is
...
when reds_t => -- illegal, but seems unambiguous enough
case reds_t'(fsm_state) is
when brown =>
fsm_state <= some_state;

when red =>
when orange =>
fsm_state <= some_state;

end case;
when blues_t'low to blues_t'high => -- wordy, but works
case blues_fsm in
...
end case;
when invalid =>
...
end;


given these declarations:

type state_t is (
black, brown, red, orange,
yellow, green, blue, violet,
gray, white, invalid
);
subtype reds_t is state_t range brown to orange;
subtype blues_t is state_t range green to violet;

signal fsm_state, some_state : state_t;
signal blues_fsm : blues_t;


======

Hi,
reds_t is just a signal name, but not a value, while blues_t'low represents an actual value.

have you tried what happens when you use

reds_t'range

??

This is often used in loops like
for i in my_slv'range loop
to get this interpreted as e.g.
for i in 31 downto 0 loop

So it might work for the case-when too.


Have a nice synthesis
Eilert
 
M

MikeWhy

Am Freitag, 27. April 2012 06:11:25 UTC+2 schrieb MikeWhy:

Hi,
reds_t is just a signal name, but not a value, while blues_t'low
represents an actual value.

have you tried what happens when you use

reds_t'range

??

This is often used in loops like
for i in my_slv'range loop
to get this interpreted as e.g.
for i in 31 downto 0 loop

So it might work for the case-when too.

Hi, yes. XST complains that reds_t is not an array.
 
A

Andy

Hi, yes. XST complains that reds_t is not an array.- Hide quoted text -

- Show quoted text -

Legal vhdl and waht XST will accept is two different things. Did you
try the code in any other, more capable tools (Synplify, modelsim,
etc.)?

Andy
 
M

MikeWhy

Andy said:
Legal vhdl and waht XST will accept is two different things. Did you
try the code in any other, more capable tools (Synplify, modelsim,
etc.)?

I am limited to the subset that XST will synthesize. Everything else has to
remain hypothetical for the moment. Does synplify accept "case <type_sig> is
when <subtype>'range =>"? No problem with in normal usage; e.g. array type
values in a loop. I just didn't know if it was a tool/language issue, or my
understanding of the language. Hence, the question.
 
H

hssig

Why don't you use the following much simpler description:



case fsm_state is
when brown | red | orange =>
when green | blue | violet =>
when others =>
end case;



Cheers, hssig
 

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