Cast natural to std_logic_vector (and the other way)

Discussion in 'VHDL' started by badwolf500, Aug 14, 2006.

  1. badwolf500

    badwolf500

    Joined:
    Aug 14, 2006
    Messages:
    1
    Hi,

    Is it possible to convert a variable of type natural to a std_logic_vector (and do the opposite). I am trying to do this and either I am not using the correct commands or the wrong library. Does anyone know how to do this?

    I have used an integer instead but would like to know if it is possible.

    Many Thanks
     
    badwolf500, Aug 14, 2006
    #1
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