"casting" bits to bits?

Discussion in 'VHDL' started by sergey, Nov 8, 2006.

  1. sergey

    sergey Guest

    Hi all again,

    Probably a stupid question, but...

    I have a signal in my testbench that's "sfixed(X downto -Y)" (sfixed
    being signed fixed from David Bishop's fixed-point library).

    When I synthesized the actual component, the synthesized model VHDL
    converted all of the sfixed to std_logic_vectors.

    How do I now map my sfixed in the testbench to std_logic_vector in the
    model? (its all just bits of the same length...)

    Thanks,

    Sergey
    sergey, Nov 8, 2006
    #1
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  2. sergey

    sergey Guest

    Yup, stupid question :) sorry guys.

    Should've looked at the fixed point manual:

    Most synthesis tools do not support any I/O format other than
    "std_logic_vector" and "std_logic". Thus, functions have been
    created to convert between std_logic_vector and ufixed or sfixed and
    vice versa:
    uf7_3 <= to_ufixed (slv7, uf7_3'high, uf7_3'low);
    and
    slv7 <= to_slv (uf7_3);

    -- Sergey


    sergey wrote:
    > Hi all again,
    >
    > Probably a stupid question, but...
    >
    > I have a signal in my testbench that's "sfixed(X downto -Y)" (sfixed
    > being signed fixed from David Bishop's fixed-point library).
    >
    > When I synthesized the actual component, the synthesized model VHDL
    > converted all of the sfixed to std_logic_vectors.
    >
    > How do I now map my sfixed in the testbench to std_logic_vector in the
    > model? (its all just bits of the same length...)
    >
    > Thanks,
    >
    > Sergey
    sergey, Nov 8, 2006
    #2
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