change initial value of state machine

Discussion in 'VHDL' started by Matt Clement, Nov 21, 2006.

  1. Matt Clement

    Matt Clement Guest

    Hello

    I have a design that has a state machine with 39 states. I would like to
    start the state machine at state 39 rather than the left most state in the
    type list. I have seen this done online and in many tutorials however it
    doesnt simulate correctly in Quartus II. Is this the proper way to define
    the initial state to start on power up?

    .....more vhdl.

    ARCHITECTURE ONE OF HALF_CLONE IS
    TYPE STATE_TYPE IS
    (IDLE,S0,S1,S2,S3,S4,S5,S6,S7,S8,S9,S10,S11,S12,S13,S14,S15,S16,S17,S18,S19,S20,S21,S22,S23,S24,S25,S26,S27,S28,S29,S30,S31,S32,S33,S34,S35,S36,S37,S38,S39);
    SIGNAL STATE1: STATE_TYPE;
    SIGNAL STATE: STATE_TYPE := S39;
    SIGNAL TEMP : STD_LOGIC_VECTOR(31 DOWNTO 0);

    ......more vhdl.

    Thanks for any help.
    Matt
    Matt Clement, Nov 21, 2006
    #1
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  2. Matt Clement

    Matt Clement Guest

    oops. guess I should actually count the # of states. Obviously the design
    snippet shows more than 39 states.
    question is still relevent.
    Matt
    Matt Clement, Nov 21, 2006
    #2
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  3. Matt Clement

    Guest

    The proper way to set the initial state is with a reset. Quartus _may_
    be getting confused about initial and default states.

    Like this:

    process(RESET, CLOCK)
    begin
    if (RESET = '1') then
    STATE <= S39;
    elsif (CLOCK'event and CLOCK = '1') then
    case STATE is
    when IDLE =>
    if somecondition then
    STATE <= S0;

    ... more code here ...
    , Nov 22, 2006
    #3
  4. Matt Clement

    kclo4 Guest

    Matt Clement a écrit :
    > Hello
    >
    > I have a design that has a state machine with 39 states. I would like to
    > start the state machine at state 39 rather than the left most state in the
    > type list. I have seen this done online and in many tutorials however it
    > doesnt simulate correctly in Quartus II. Is this the proper way to define
    > the initial state to start on power up?
    >
    > ....more vhdl.
    >
    > ARCHITECTURE ONE OF HALF_CLONE IS
    > TYPE STATE_TYPE IS
    > (IDLE,S0,S1,S2,S3,S4,S5,S6,S7,S8,S9,S10,S11,S12,S13,S14,S15,S16,S17,S18,S19,S20,S21,S22,S23,S24,S25,S26,S27,S28,S29,S30,S31,S32,S33,S34,S35,S36,S37,S38,S39);
    > SIGNAL STATE1: STATE_TYPE;
    > SIGNAL STATE: STATE_TYPE := S39;
    > SIGNAL TEMP : STD_LOGIC_VECTOR(31 DOWNTO 0);
    >
    > .....more vhdl.
    >
    > Thanks for any help.
    > Matt
    >
    >

    It will works ... in simulation but never on board because the first
    initialisation :=S39 of a variable or a signal is just use by the sim
    tool but not synthetizer.
    You should define your initial state by a reset and I personnaly always
    add a case others when I write a state machine

    ex:

    > ....more vhdl.
    >
    > ARCHITECTURE ONE OF HALF_CLONE IS
    > TYPE STATE_TYPE IS
    >

    (IDLE,S0,S1,S2,S3,S4,S5,S6,S7,S8,S9,S10,S11,S12,S13,S14,S15,S16,S17,S18,S19,S20,S21,S22,S23,S24,S25,S26,S27,S28,S29,S30,S31,S32,S33,S34,S35,S36,S37,S38,S39);
    > SIGNAL STATE1: STATE_TYPE;
    > SIGNAL STATE: STATE_TYPE := S39;
    > SIGNAL TEMP : STD_LOGIC_VECTOR(31 DOWNTO 0);
    >
    > .....more vhdl.


    process(clk,rst)
    begin
    if rst = '1'then
    state <= S39;
    elsif rising_edge(clk) then
    case state is
    when IDLE =>
    ....
    when S0 =>
    ....
    when S39 =>
    ....
    when others =>
    state <= S39;
    end case;


    end if;
    end process;

    like this you should avoid any trouble


    alexis
    kclo4, Nov 22, 2006
    #4
  5. Matt Clement

    Matt Clement Guest

    Here is my delima
    The board is already in production so I am trying to create a firmware
    "update" that will allow my board to start up in a state that is different
    than the left most in the list. I cannot add additional hardware on board
    without a redesign of the board itself. I was trying to correct the problem
    purely in VHDL. I also cannot change the way the pins are mapped without
    rendering the board useless. I figured if I was able to start it in an
    unused state then maybe I could do my initialization in that state and never
    return to that state once started. Is there any other options/approaches to
    this constrained problem? I need to set a signal to ones on initial power
    up of the board and then start the normal operations where the signal can be
    manipulated.

    Thanks
    Matt



    "kclo4" <> wrote in message
    news:ek0vjb$j9f$...
    > Matt Clement a écrit :
    >> Hello
    >>
    >> I have a design that has a state machine with 39 states. I would like to
    >> start the state machine at state 39 rather than the left most state in
    >> the type list. I have seen this done online and in many tutorials
    >> however it doesnt simulate correctly in Quartus II. Is this the proper
    >> way to define the initial state to start on power up?
    >>
    >> ....more vhdl.
    >>
    >> ARCHITECTURE ONE OF HALF_CLONE IS
    >> TYPE STATE_TYPE IS
    >> (IDLE,S0,S1,S2,S3,S4,S5,S6,S7,S8,S9,S10,S11,S12,S13,S14,S15,S16,S17,S18,S19,S20,S21,S22,S23,S24,S25,S26,S27,S28,S29,S30,S31,S32,S33,S34,S35,S36,S37,S38,S39);
    >> SIGNAL STATE1: STATE_TYPE;
    >> SIGNAL STATE: STATE_TYPE := S39;
    >> SIGNAL TEMP : STD_LOGIC_VECTOR(31 DOWNTO 0);
    >>
    >> .....more vhdl.
    >>
    >> Thanks for any help.
    >> Matt
    >>
    >>

    > It will works ... in simulation but never on board because the first
    > initialisation :=S39 of a variable or a signal is just use by the sim tool
    > but not synthetizer.
    > You should define your initial state by a reset and I personnaly always
    > add a case others when I write a state machine
    >
    > ex:
    >
    > > ....more vhdl.
    > >
    > > ARCHITECTURE ONE OF HALF_CLONE IS
    > > TYPE STATE_TYPE IS
    > >

    > (IDLE,S0,S1,S2,S3,S4,S5,S6,S7,S8,S9,S10,S11,S12,S13,S14,S15,S16,S17,S18,S19,S20,S21,S22,S23,S24,S25,S26,S27,S28,S29,S30,S31,S32,S33,S34,S35,S36,S37,S38,S39);
    > > SIGNAL STATE1: STATE_TYPE;
    > > SIGNAL STATE: STATE_TYPE := S39;
    > > SIGNAL TEMP : STD_LOGIC_VECTOR(31 DOWNTO 0);
    > >
    > > .....more vhdl.

    >
    > process(clk,rst)
    > begin
    > if rst = '1'then
    > state <= S39;
    > elsif rising_edge(clk) then
    > case state is
    > when IDLE =>
    > ....
    > when S0 =>
    > ...
    > when S39 =>
    > ...
    > when others =>
    > state <= S39;
    > end case;
    >
    >
    > end if;
    > end process;
    >
    > like this you should avoid any trouble
    >
    >
    > alexis
    >
    >
    Matt Clement, Nov 22, 2006
    #5
  6. Matt Clement wrote:

    > The board is already in production so I am trying to create a firmware
    > "update" that will allow my board to start up in a state that is different
    > than the left most in the list.


    Add a register to the design that
    counts up to N and stops.
    Create an internal reset pulse by
    decoding one of these counts.

    If you are lucky, the device
    will start the count at zero for you
    without a reset.

    Good luck.

    -- Mike Treseler
    Mike Treseler, Nov 22, 2006
    #6
  7. Matt Clement

    Guest

    You mentioned Quartus-II, so I'm guessing you're using "Brand-A" parts.

    I'm also guessing that you don't have a system reset handy, which is
    causing you greif.

    Most "Brand-A" parts have a concept of a power-on reset. And IIRC, the
    synthesizer selects the first enumerated value of the state in the
    declaration as the POR value. I also seem to remember that the
    initalizer is only honored for signals that do _not_ change.

    In your case, it _might_ be as simple as reordering your states as
    (S39, IDLE, S0, S1, etc.) Or more legibly, (POR, IDLE, S0, S1, ....
    S39)

    And I also think that you're dicovering all kinds of new adjectives to
    describe a synchronous circuit that's built without a reset. :)

    GH
    , Nov 22, 2006
    #7
  8. Matt Clement

    Matt Clement Guest

    Indeed GH you are correct with the colorful phrases. I also have changed
    ,prior to your reply, the order to list S39 as the left most state and then
    I do my reset in that state, but it requires me to wait until the first
    clock cycle before it initializes. I would prefer to have it initialize
    without waiting for a clock input. If I put a sequencial statement before
    the process(FSM) will it only execute the first time it runs or each time?
    It seems that maybe I can initialize them before the process and should only
    return to the process on each event??

    Thanks
    Matt


    <> wrote in message
    news:...
    > You mentioned Quartus-II, so I'm guessing you're using "Brand-A" parts.
    >
    > I'm also guessing that you don't have a system reset handy, which is
    > causing you greif.
    >
    > Most "Brand-A" parts have a concept of a power-on reset. And IIRC, the
    > synthesizer selects the first enumerated value of the state in the
    > declaration as the POR value. I also seem to remember that the
    > initalizer is only honored for signals that do _not_ change.
    >
    > In your case, it _might_ be as simple as reordering your states as
    > (S39, IDLE, S0, S1, etc.) Or more legibly, (POR, IDLE, S0, S1, ....
    > S39)
    >
    > And I also think that you're dicovering all kinds of new adjectives to
    > describe a synchronous circuit that's built without a reset. :)
    >
    > GH
    >
    Matt Clement, Nov 22, 2006
    #8
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