change variable in case statement

Discussion in 'VHDL' started by vtbvtb, Sep 11, 2012.

  1. vtbvtb

    vtbvtb Guest

    Hello,

    I have a problem with logic of case statement in vhdl. I wonder is the variable that selects the case condition can be changed within the statement. To clarify:

    process(clk)

    variable aaa: std_logic_vector(2 downto 0):="000";

    case aaa is

    when "000" =>
    if () then
    something
    end if;
    aaa := aaa+1;

    when "001" =>
    something something


    when VALUE_4 to VALUE_N =>
    -- sequential statements

    when others =>
    -- sequential statements

    end case ;
    vtbvtb, Sep 11, 2012
    #1
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