Character Map with Xilinx FPGA

Discussion in 'VHDL' started by usenet, Jul 22, 2006.

  1. usenet

    usenet Guest

    Hello,

    I'm trying to display text via the vga port of my xilinx spartan-3. The
    question is how do I do it. I now that I have to generate a character-map or
    a character rom. But has some one experience with this, i.e. some vhdl code,
    and how do I do this with modelsim.

    I already searched with google and either I'm too dumb or there is nothing
    helpful out there. So how do I code the characters into vhdl with modelsim
    so that it will be synthesized on a spartan-3. Has someone a coding example?

    Thanks in advance
     
    usenet, Jul 22, 2006
    #1
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  2. "usenet" <> writes:

    > Hello,
    >
    > I'm trying to display text via the vga port of my xilinx spartan-3. The
    > question is how do I do it. I now that I have to generate a character-map or
    > a character rom. But has some one experience with this, i.e. some vhdl code,
    > and how do I do this with modelsim.
    >


    Do you have the bitmaps you want to use?
    Assuming they are simple 8 bit wide characters with the same number of
    rows (let's say 8 for this exambple) in each you can do:
    constant char_rom : integer range 0 to 255 := (
    0,0,0,0,0,0,0,0, -- space char
    <<<row 1 of !>>>, <<<row 2 of !>>>, etc for !
    <<<row 1 of ">>>, <<<row 2 of ">>>, etc for "
    etc for whole of ASCII set
    );


    Then if you want the values for the character in signal c:
    char_rom(c-character'pos(' ')) is the first row
    char_rom(c-character'pos(' ')+1) is the second row

    [Ahh, the days of defining user defined characters on the Beeb with VDU
    commands come flooding back :)]

    HTH!

    Martin

    --

    TRW Conekt - Consultancy in Engineering, Knowledge and Technology
    http://www.trw.com/conekt
     
    Martin Thompson, Jul 24, 2006
    #2
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  3. usenet

    usenet Guest

    Thanks for the answer but I solved it on my own. Anyway, I will post it
    here:

    signal addr : std_logic_VECTOR(8 downto 0);

    type ram_t is array (0 to 511) of std_logic_vector(7 downto 0);

    -- place characters inside the ram. Each letter consists of 8 rows.

    signal ram : ram_t :=

    (

    "00111100",

    "01100110",

    ..

    ..

    ..

    "00000000"

    );

    ..

    ..

    ..

    -- read the ram and display it to dout

    dout <= ram(conv_integer(addr));





    Have I nice day

    Da Unseen
     
    usenet, Jul 26, 2006
    #3
  4. "usenet" <> writes:

    > Thanks for the answer but I solved it on my own. Anyway, I will post it
    > here:
    >


    Excellent!
    <snip>
    >
    > dout <= ram(conv_integer(addr));
    >


    This looks like some std_logic_arith... this is a very out-of-date
    coding style, you should be using ieee.numeric_std these days as it's
    a proper standard and better behaved than the Synopsys libraries that
    they (inexplicably) compiled into the ieee lib.

    See the VHDL FAQ for the detailed reasons why.

    Cheers,
    Martin

    --

    TRW Conekt - Consultancy in Engineering, Knowledge and Technology
    http://www.trw.com/conekt
     
    Martin Thompson, Jul 26, 2006
    #4
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