Character syntax

Discussion in 'VHDL' started by Daniel, Dec 29, 2004.

  1. Daniel

    Daniel Guest

    Hi all!
    I can't find the correct syntax when I use the "carriage return" character.

    Someone that can help me?

    Greetings from Daniel!


    library IEEE;
    use IEEE.STD_LOGIC_1164.all;

    entity test_string is
    port(
    dummy_in : in std_logic;
    dummy_out : out std_logic);
    end test_string;

    architecture rtl of test_string is

    subtype string_type is string (1 to 2);
    signal test_string: string_type;

    begin

    test_string(1)<='d'; --ok

    --trying with "carriage return"
    test_string(2)<=cr; --error. Syntax help please!

    end rtl;
    Daniel, Dec 29, 2004
    #1
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  2. Daniel

    Dave Higton Guest

    In message <>
    (Daniel) wrote:

    > --trying with "carriage return"
    > test_string(2)<=cr; --error. Syntax help please!


    This won't work unless you define cr somewhere. The tools have no
    built-in knowledge of the abbreviations for the control characters.

    Dave
    Dave Higton, Dec 29, 2004
    #2
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  3. Daniel

    Jim Lewis Guest

    Daniel,
    Assuming you were testing this in a simulator and
    not a synthesis tool, your example should have
    been fine. Just to remove any doubt of the other
    person who replied, ...

    type character is (
    nul, soh, stx, etx, eot, enq, ack, bel,
    bs, ht, lf, vt, ff, cr, soe, si,
    dle, dc1, dc2, dc3, dc4, nak, syn, tb,
    can, em, sub, esc, fsp, gsp, rsp, usp,

    ' ', '!', '"', '#', '$', '%', '&', ''',
    '(', ')', '*', '+', ',', '-', '.', '/',
    '0', '1', '2', '3', '4', '5', '6', '7',
    '8', '9', ':', ';', '<', '=', '>', '?',

    '@', 'A', 'B',
    . . .

    CR is most certainly a permitted identifier to be used
    as a character. I have never put one in a string
    object, I have always added things like this when I
    was using report and such. In addition, I don't use CR,
    I use LF. I also use them upper case, however, note the
    definitions are lower case, so that should not be
    an issue.

    If you were in a synthesis tool, there is no reason to
    expect it to understand a string of any form.

    Cheers,
    Jim


    > Hi all!
    > I can't find the correct syntax when I use the "carriage return" character.
    >
    > Someone that can help me?
    >
    > Greetings from Daniel!
    >
    >
    > library IEEE;
    > use IEEE.STD_LOGIC_1164.all;
    >
    > entity test_string is
    > port(
    > dummy_in : in std_logic;
    > dummy_out : out std_logic);
    > end test_string;
    >
    > architecture rtl of test_string is
    >
    > subtype string_type is string (1 to 2);
    > signal test_string: string_type;
    >
    > begin
    >
    > test_string(1)<='d'; --ok
    >
    > --trying with "carriage return"
    > test_string(2)<=cr; --error. Syntax help please!
    >
    > end rtl;



    --
    ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
    Jim Lewis
    Director of Training mailto:
    SynthWorks Design Inc. http://www.SynthWorks.com
    1-503-590-4787

    Expert VHDL Training for Hardware Design and Verification
    ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
    Jim Lewis, Dec 29, 2004
    #3
  4. Daniel

    Rob Dekker Guest

    "Jim Lewis" <> wrote in message news:...
    [..]
    > > --trying with "carriage return"
    > > test_string(2)<=cr; --error. Syntax help please!

    [...]
    > Daniel,
    > Assuming you were testing this in a simulator and
    > not a synthesis tool, your example should have
    > been fine.


    Actually, all VHDL tools (synthesis or simulation or otherwize) should also be able to handle this.
    It's a simple use of a literal, defined in the std.standard package.

    If you get a syntax error, file a bug-report with the tool vendor.

    Rob
    Rob Dekker, Dec 29, 2004
    #4
  5. Daniel

    ispir Guest

    hi all,

    i'm not sure but isn't that a problem: entity name (test_string) and
    signal name are same.

    thanks
    mustafa
    ispir, Jan 10, 2005
    #5
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