Check all bits set

[aleksazr]

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

signal WRaddr : unsigned(11 downto 0);

if rising_edge(CLK) then
if WRaddr/="111111111111" then
WRaddr <= WRaddr +1;
end if;
end if;

How do I write this so I can easily
change the length of WRaddr?

TIA

 

[Enrik Berkhan]

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

signal WRaddr : unsigned(11 downto 0);

if rising_edge(CLK) then
if WRaddr/="111111111111" then
WRaddr <= WRaddr +1;
end if;
end if;

How do I write this so I can easily
change the length of WRaddr?

You could use a constant like

constant WRaddr_all_ones: unsigned(WRaddr'range) := (others => '1');

Enrik

 

[Gabor]

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

signal WRaddr : unsigned(11 downto 0);

if rising_edge(CLK) then
if WRaddr/="111111111111" then
WRaddr <= WRaddr +1;
end if;
end if;

How do I write this so I can easily
change the length of WRaddr?

TIA

how about

if WRaddr /= (others => '1') then
.. . .

-- Gabor

 

[aleksazr]

how about

if WRaddr /= (others => '1') then
. . .

-- Gabor

That was my first guess, but ISE 13.3 doesn't like it:
Can not determine the "others" values in aggregate. (LRM 7.3.2.2)

 

[aleksazr]

You could use a constant like

constant WRaddr_all_ones: unsigned(WRaddr'range) := (others => '1');

Enrik

That works, thanks

 

[Gabor]

That works, thanks

Good point. I missed the declaration type "unsigned". My
code would have worked for std_logic_vector.

Regards,
Gabor

 

[Nicolas Matringe]

Le 22/06/2012 20:14, Gabor a écrit :

Good point. I missed the declaration type "unsigned". My
code would have worked for std_logic_vector.

I don't think so. Please give it a try.

Another solution would be

if WRaddr /= (WRaddr'range => '1') then


Nicolas

 

[Andy]

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

signal WRaddr : unsigned(11 downto 0);

if rising_edge(CLK) then
    if WRaddr/="111111111111" then
        WRaddr <= WRaddr +1;
    end if;
end if;

How do I write this so I can easily
change the length of WRaddr?

TIA

if WRaddr /= 2**WRaddr'length - 1 then -- unsigned/natural compare

if WRaddr /= unsigned'(WRaddr'range => '1') then

Andy

 

[Jim]

if not(WRaddr) /= 0 then

Jim

P.S.
At one time Synopsys DC (ASIC synthesis) gave an error on
having expressions with 'range, like this (although the
language definitely allows it):
if WRaddr /= (WRaddr'range => '1') then

Anyone try this more recently on DC?

 

[Ralf Hildebrandt]

Hi!

if WRaddr/="111111111111" then

How do I write this so I can easily
change the length of WRaddr?

if (signed(WRaddr) /= -1) then -- check if all bits set


I would recommend to add the comment, because if "-1" has no meaning for
the usual behavior of WRaddr this code might confuse a colleague. On the
other hand it is very clear to read and uses only very basic VHDL
features (from Numeric_Std package).

Ralf

 

[aleksazr]

Hi!



if (signed(WRaddr) /= -1) then -- check if all bits set


I would recommend to add the comment, because if "-1" has no meaning for
the usual behavior of WRaddr this code might confuse a colleague. On the
other hand it is very clear to read and uses only very basic VHDL
features (from Numeric_Std package).

Ralf

Thats how I do things in C... cool, thanks