chip scope

Discussion in 'VHDL' started by u_stadler@yahoo.de, Mar 21, 2008.

  1. Guest

    hi

    i have a question. i have an edk project that i want to debug. so i
    inserted a chipscope core. my question now is if there is a way to
    look a signals not in the top level entities. for example i have an ip
    core connected to the fsl bus. but if i want to have a look at some
    signal withing the ip core i have to put some debug signals all the
    way up to the top level entity in my ip. is there another way to do
    that?


    thanks
    urban
     
    , Mar 21, 2008
    #1
    1. Advertising

Want to reply to this thread or ask your own question?

It takes just 2 minutes to sign up (and it's free!). Just click the sign up button to choose a username and then you can ask your own questions on the forum.
Similar Threads
  1. Charles M. Elias

    Re: I/Os with Cypress chip

    Charles M. Elias, Jul 16, 2003, in forum: VHDL
    Replies:
    1
    Views:
    1,334
    Charles M. Elias
    Jul 18, 2003
  2. y_p_w
    Replies:
    9
    Views:
    1,107
    y_p_w
    Aug 8, 2003
  3. pandora
    Replies:
    0
    Views:
    569
    pandora
    Apr 14, 2004
  4. GSK1976
    Replies:
    0
    Views:
    429
    GSK1976
    Jul 31, 2004
  5. Derek Simmons
    Replies:
    1
    Views:
    556
    Derek Simmons
    Mar 31, 2005
Loading...

Share This Page