Choosing the "right" main clock for a design

[Ronny Ramone]

Hi !

have a some questions regarding good design practice on how to choose the "right" clock(s) for a design.

I have a design where most of my logic can run on 80MHz, but small parts of it needs a 2x clock. Most likely I will put a 80MHz oscillator with the possibility of a 2x multiplier(DCM).

So then my questions are:

1. Should I run the whole design on 160MHz and divide all 80MHz processes (state machines etc.) down by two ?

2. Should I use two clock domains(80 and 160) and then deal with synchronizing between the domains afterwards ?

3. I have one state machine that should interact with a async. SRAM witch has a max. readout speed of 80MHz. Most of this state machine can run on 80MHz, but I need to toggle a latch signal to the RAM within the 80 MHz readout cycle. Should this state machine run on 160 ? If so, I need to divide down almost all the states except for the one that deals with the latching. Or should I make a separate process on 160MHz that deals with this latching ?

Answers to my question and maybe some general rules of thumb on this issue will be greatly appreciated !

 

[scottcarl]

Hi !

have a some questions regarding good design practice on how to choose the "right" clock(s) for a design.

I have a design where most of my logic can run on 80MHz, but small parts of it needs a 2x clock. Most likely I will put a 80MHz oscillator with the possibility of a 2x multiplier(DCM).

So then my questions are:

1. Should I run the whole design on 160MHz and divide all 80MHz processes (state machines etc.) down by two ?

2. Should I use two clock domains(80 and 160) and then deal with synchronizing between the domains afterwards ?

3. I have one state machine that should interact with a async. SRAM witch has a max. readout speed of 80MHz. Most of this state machine can run on 80MHz, but I need to toggle a latch signal to the RAM within the 80 MHz readout cycle. Should this state machine run on 160 ? If so, I need to divide down almost all the states except for the one that deals with the latching. Or should I make a separate process on 160MHz that deals with this latching ?

Answers to my question and maybe some general rules of thumb on this issue will be greatly appreciated !

Good questions here,
For 1) You should try and use the slower clock whenever possible to reduce power consumption. Slower clocking may also simulate faster by not having to execute as many steps throught your sim.

2) The DCMS/PLLs within Xilinx/Altera were built to synchronize multiple clock domains so definitely use them, they are great. Create this 2x (160MHz) clock from the same DCM/PLL and it will be automatically phase aligned with the outgoing 1x (80MHz) clock. You will not have much difficulty meeting timing asynchrnous issues when you move signals from one domain to the other.

3) I would suggest running most of this state machine at 80Mhz (if you're indicating that the inputs to it are also on the 80MHz clock domain). Then in your one state that needs to create a sub 12.5ns pulse you can port that one signal over to a process running at 160MHz. This will make it a little easier to read and keep things seperated.

Scott C