clk event at firs simulation cycle

[valtih1978]

signal w_clk : std_logic := '1' ;

The clock condition does not pass on the first sim cycle in Modelsim. Why?

read_stimuli : process(w_clk)
if(w_clk'event and w_clk='1') then

 

[Nicolas Matringe]

Le 04/09/2012 14:03, valtih1978 a écrit :

signal w_clk : std_logic := '1' ;

The clock condition does not pass on the first sim cycle in Modelsim. Why?

read_stimuli : process(w_clk)
if(w_clk'event and w_clk='1') then

Because there's no event on clock.
Assigning a default value in the declaration doesn't generate en event.

Nicolas

 

[valtih1978]

Because LRM has the following section?

The initialization phase consists of the following steps:
c) The signals in the model are updated as follows inan order such that
if a given signal R depends upon the current value of another signal S,
then the current value of S is updated prior to the updat-ing of the
current value of R:
— The driving value and the effective value of eachexplicitly declared
signal are computed, and the variables representing the driving value
and current value of the signal are set to the driving value and
effective value, respectively. The current value is assumed to have been
the value of the signal for an infinite length of time prior to the
start of simulation. If a force, deposit, or release was scheduled for
any driver or signal, the force, deposit or release is no longer
sched-uled for the driver or signal.
— The value of each implicit signal of the formS'STABLE(T) or S'QUIET(T)
is set to TRUE. The value of each implicit signal of the form
S'DELAYED(T) is set to the initial value of its prefix, S.

 

[Gabor]

Because LRM has the following section?

The initialization phase consists of the following steps:
c) The signals in the model are updated as follows inan order such that
if a given signal R depends upon the current value of another signal S,
then the current value of S is updated prior to the updat-ing of the
current value of R:
— The driving value and the effective value of eachexplicitly declared
signal are computed, and the variables representing the driving value
and current value of the signal are set to the driving value and
effective value, respectively. The current value is assumed to have been
the value of the signal for an infinite length of time prior to the
start of simulation. If a force, deposit, or release was scheduled for
any driver or signal, the force, deposit or release is no longer
sched-uled for the driver or signal.
— The value of each implicit signal of the formS'STABLE(T) or S'QUIET(T)
is set to TRUE. The value of each implicit signal of the form
S'DELAYED(T) is set to the initial value of its prefix, S.

"The current value is assumed to have been the value of the signal for
an infinite length of time prior to the start of simulation."

That seems to state pretty clearly that there is no event at time zero.
You could of course use a process to start the clock at time zero,
and it would create an event - going from undefined to 1 (assuming
you don't initialize the clock to 1 in the declaration).

-- Gabor