clock devide by 1.5

Discussion in 'VHDL' started by aaaaaa, Feb 23, 2005.

  1. aaaaaa

    aaaaaa Guest

    Hi guyes,
    can any body suggest the logic for a clock device by 1.5 .
    Input clock frequency is 4 Mhz. and the target device is ALTERA
    EP1C3T100C-8 .
    Thanx in advance .
     
    aaaaaa, Feb 23, 2005
    #1
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  2. aaaaaa

    Jezwold Guest

    Just recently been discussed on here,use search to find fractional
    divider.
     
    Jezwold, Feb 23, 2005
    #2
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  3. On Wed, 23 Feb 2005 00:18:31 -0500, "aaaaaa" <> wrote:

    >Hi guyes,
    >can any body suggest the logic for a clock device by 1.5 .
    >Input clock frequency is 4 Mhz. and the target device is ALTERA
    >EP1C3T100C-8 .
    >Thanx in advance .


    http://www.xilinx.com/xcell/xl33/xl33_30.pdf

    Regards,
    Allan
     
    Allan Herriman, Feb 23, 2005
    #3
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