clock divide by 5

Discussion in 'VHDL' started by pdjuandi, Mar 16, 2009.

  1. pdjuandi

    pdjuandi

    Joined:
    Mar 16, 2009
    Messages:
    1
    Hi,

    I want to generate a clock which is a divide of 5 from an input clock and with symmetrical duty cycle. Can anyone help me with the vhdl codes? I'm new with VHDL.

    Thank you.
     
    pdjuandi, Mar 16, 2009
    #1
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  2. pdjuandi

    twinkle

    Joined:
    Feb 9, 2009
    Messages:
    3
    The following code would give u some idea

    The following code explains how to generate a slower clock from a faster clock. That means it is exactly opposite to clock divider. But I think this would give u some idea about how to make the clock divider.


    -----------------------------------------------------------------------------
    -- Clk Generator
    -----------------------------------------------------------------------------
    library ieee;
    use ieee.std_logic_1164.all;
    use ieee.std_logic_signed.all;
    use ieee.std_logic_arith.all;


    entity clk_gen is
    port (
    FClk : in std_logic;
    SClk : out std_logic

    );
    end clk_gen;

    architecture behavioral of clk_gen is

    begin
    process (FClk)
    VARIABLE temp : std_logic_vector(2 downto 0):= "000";
    begin
    IF (FClk'event and FClk = '1') THEN
    temp := temp + '1';
    SClk <= temp(2);
    END IF;
    end process;
    end behavioral;


    --FClk means faster clock
    --SClk means slower clock
     
    twinkle, Mar 17, 2009
    #2
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  3. pdjuandi

    JohnDuq

    Joined:
    Dec 9, 2008
    Messages:
    88
    You are not going to get a 50% duty cycle (2.5/5) unless you can first double your clock and then divide by 10. Do you have a PLL available in your IC?
     
    JohnDuq, Mar 18, 2009
    #3
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