clock divide by n (n is variable)

Discussion in 'VHDL' started by rnpatil, Apr 27, 2009.

  1. rnpatil

    rnpatil

    Joined:
    Apr 27, 2009
    Messages:
    2
    Hi all
    I want to divide input clock, as per requirment the divide value n is going to vary between 2 to 16. Please guide me how to implement it in vhdl
     
    rnpatil, Apr 27, 2009
    #1
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  2. rnpatil

    jeppe

    Joined:
    Mar 10, 2008
    Messages:
    348
    Location:
    Denmark
    Try this

    Code:
    process( Clk_in)
        variable ScaleCount: Std_logic_vector( 4 downto 0) := "00000";
    begin
        if Rising_edge( Clk_in) then
           Clk_Out <= '0';
           ScaleCount := ScaleCount+1;
           if ScaleCount=Scale then
              Clk_out <= '1';
              ScaleCount := "00000";
           end if;
       end if;
    end process;
    Your welcome
    Jeppe
     
    jeppe, Apr 27, 2009
    #2
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  3. rnpatil

    rnpatil

    Joined:
    Apr 27, 2009
    Messages:
    2
    Thankx Jeppe
    the code works fine for 00010 (i.e. divide by 2), but for other divide counts like 3,4,...., duty cycle (50%) is not maintained, I tried to modify the code to maintain the 50% duty cycle, then clk gets divided by twice the count and 50% duty cycle gets maintained. Is any sol'n to maintain 50% duty cycle.
     
    rnpatil, Apr 28, 2009
    #3
  4. rnpatil

    JohnDuq

    Joined:
    Dec 9, 2008
    Messages:
    88
    You will only get 50% duty cycle when your divider is even. If you can double your clock first (use both clock edges?) then you can double your divider and keep even dividers (1 -> 2, 2 -> 4, 3-> 6...). Note that this will introduce clock jitter because your main clock won't be EXACTLY 50% duty cycle. If that is a concern you need to use a device with a PLL to increase the clock frequency.
     
    JohnDuq, Apr 28, 2009
    #4
  5. rnpatil

    surpriya.7

    Joined:
    Mar 24, 2009
    Messages:
    5
    Please try this:

    Code:
    entity clk_div is
        Port ( clk : in  STD_LOGIC;
    			  div: in STD_LOGIC_VECTOR(3 downto 0);
               div_clk : out  STD_LOGIC);
    end clk_div;
    
    architecture Behavioral of clk_div is
    signal var: STD_LOGIC_VECTOR(15 downto 0):= (others => '0');
    begin
    
    
    	process(clk)
    	begin
    	
    		if(clk'event and clk = '1') then
    			var <= var + '1';
    		end if;
    		
    		if(clk'event and clk = '0') then
    			var <= var + '1';
    		end if;
    		
    		div_clk <= var(conv_integer(div));
    		
    	end process;
    end Behavioral;
    
     
    Last edited: Apr 29, 2009
    surpriya.7, Apr 29, 2009
    #5
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