clock divider by 2

[martstev]

this may be the simplest question..
I want to write a clock divider by 2 using DFF...but I just want to use
1 DFF when /Q is connected to the data_in

so the inputs are clock and data_in and outputs are Q and /Q
and /Q is connected to data_in.

how can I write this in VHDL or Can I?

Thank you,
Martin

 

[Thomas Stanka]

this may be the simplest question..
I want to write a clock divider by 2 using DFF...but I just want to use
1 DFF when /Q is connected to the data_in

so the inputs are clock and data_in and outputs are Q and /Q
and /Q is connected to data_in.

how can I write this in VHDL or Can I?

To get exactly what your are describing might require some more effort
(as synthesis will more likely use a D-FF with inverter), but following
lines inside your clocked process template will do a simple clk/2
divider.

if rising_edge(clk) then
data<=not data;
end if;

You should be aware that data is not phase alligned to clk, so if you
use data as a clock, you have to consider all parts clocked with data
as asynchronous to clk.

bye Thomas

 

[backhus]

this may be the simplest question..
I want to write a clock divider by 2 using DFF...but I just want to use
1 DFF when /Q is connected to the data_in

so the inputs are clock and data_in and outputs are Q and /Q
and /Q is connected to data_in.

how can I write this in VHDL or Can I?

Thank you,
Martin

Hi Martin,
If you know exactly what you are doing, you can instantiate the dff
directly from your tech library.

e.g. (using direct instantiation from techlib)

clockdivider: entity techlib.DFF
port map(c => clock,
d => feedback,
q => divided_clock,
qn => feedback);

....something like this.

If you are not really familiar with the elements of your technology
library, or if you need a generic solution do it the way as shown by
Thomas. If the synthesis tool generates an Inverter, but you are sure
that the FF has a notQ output, then try some constrainting the area or
whatever your tool offers.

have a nice synthesis
Eilert

 

[arant]

Hey Martin.

you can use the following code snippet
-------------------------RTL----------------------------
library ieee;
use ieee.std_logic_1164.all;

library divby2;
use divby2.all;

entity divby2 is
port (
clk : in std_logic;
reset : in std_logic;
clk_div2 : out std_logic
);
end divby2 ;

architecture rtl of divby2 is
signal clk_s : std_logic;

begin

p_divby2 : process(clk,reset)
begin
if (reset = '0') then
clk_s <= '0';
elsif (clk'event and clk = '1') then
clk_s <= not (clk_s);
end if;
end process p_divby2;

clk_div2 <= clk_s;

end rtl;
-----------------------------
-------------TESTBENCH--------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

library pattern;
use pattern.all;

entity test_divby2 is
end test_divby2;

architecture tb of test_divby2 is

signal logic0 : std_logic := '0';
signal logic1 : std_logic := '1';
signal clk_s : std_logic := '0';
signal reset_s : std_logic := '0';
signal clk_div2_s : std_logic;

component divby2
port (
clk : in std_logic;
reset : in std_logic;
clk_div2 : out std_logic
);
end component;

begin
reset_s <= '1' after 3 ns;

process (reset_s,clk_s)
begin
if reset_s ='1' then
clk_s <= not(clk_s) after 10 ns;
else
clk_s <= '0';
end if;
end process;

i_divby2 : divby2
port map (
clk => clk_s ,
reset => reset_s,
clk_div2 => clk_div2_s
);
end tb;
--------------------------

I think DC will put in a structure with the D flop output connected to
an inverter (in case Qn is not available ) and fed back to the input of
the D flop

Regards,
Arant