clock divider

F

FP

How do I design a clock divider without using initial conditions. I
designed once using initial values but they dont mean anything in
synthesis.

Thanks in advance for your help
 
K

KJ

How do I design a clock divider without using initial conditions.

With a reset signal.
I designed once using initial values but they dont mean anything in
synthesis.
If your targetted part has a specified power up state and the tools
that you choose to use support initial values then initial values will
work just fine.

KJ
 

Ask a Question

Want to reply to this thread or ask your own question?

You'll need to choose a username for the site, which only take a couple of moments. After that, you can post your question and our members will help you out.

Ask a Question

Members online

No members online now.

Forum statistics

Threads
473,744
Messages
2,569,484
Members
44,903
Latest member
orderPeak8CBDGummies

Latest Threads

Top