clock divider

Discussion in 'VHDL' started by FP, Jun 2, 2008.

  1. FP

    FP Guest

    How do I design a clock divider without using initial conditions. I
    designed once using initial values but they dont mean anything in
    synthesis.

    Thanks in advance for your help
     
    FP, Jun 2, 2008
    #1
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  2. FP

    KJ Guest

    On Jun 2, 4:10 pm, FP <> wrote:
    > How do I design a clock divider without using initial conditions.


    With a reset signal.

    > I designed once using initial values but they dont mean anything in
    > synthesis.
    >

    If your targetted part has a specified power up state and the tools
    that you choose to use support initial values then initial values will
    work just fine.

    KJ
     
    KJ, Jun 2, 2008
    #2
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