clock-domain-crossing simulation in Altera

Discussion in 'VHDL' started by kpram, Nov 15, 2007.

  1. kpram

    kpram

    Joined:
    Nov 15, 2007
    Messages:
    1
    Hi all

    Does anyone knows of a way to tell Quartus that a particular FF is a clock-domain-crossing FF so that post-route netlist instantiates a FF for that, which does not propagate "X".

    In Xilinx this is done by applying the ASYNC_REG attribute. But haven't found anything similar in Altera.

    regards,

    Kostas
     
    kpram, Nov 15, 2007
    #1
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