clock-domain-crossing simulation in Altera

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Hi all

Does anyone knows of a way to tell Quartus that a particular FF is a clock-domain-crossing FF so that post-route netlist instantiates a FF for that, which does not propagate "X".

In Xilinx this is done by applying the ASYNC_REG attribute. But haven't found anything similar in Altera.

regards,

Kostas
 

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